* MA 02111-1307 USA
*/
-
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
-
/* 16KB is the maximum size of instruction and data caches on
* MIPS 4K.
*/
#define MIPS_MAX_CACHE_SIZE 0x4000
-
/*
* cacheop macro to automate cache operations
* first some helpers...
li t4, CFG_CACHELINE_SIZE
move t5, t4
-
li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero.
li a0, KSEG1
addu a1, a0, v0
-
-2: sw zero, 0(a0)
+2:
+ sw zero, 0(a0)
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
mtc0 zero, CP0_TAGLO
- /*
- * The caches are probably in an indeterminate state,
- * so we force good parity into them by doing an
- * invalidate, load/fill, invalidate for each line.
- */
+ /*
+ * The caches are probably in an indeterminate state,
+ * so we force good parity into them by doing an
+ * invalidate, load/fill, invalidate for each line.
+ */
/* Assume bottom of RAM will generate good parity for the cache.
*/
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
- j ra
- .end mips_cache_reset
+ j ra
+ .end mips_cache_reset
/*******************************************************************************
*
andi v0, v0, 1
j ra
- .end dcache_status
+ .end dcache_status
/*******************************************************************************
*
li t1, -8
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
- mtc0 t0, CP0_CONFIG
+ mtc0 t0, CP0_CONFIG
j ra
- .end dcache_disable
-
+ .end dcache_disable
+#ifdef CFG_INIT_RAM_LOCK_MIPS
/*******************************************************************************
*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
icacheop(a0,a1,a2,a3,0x1d)
j ra
+
.end mips_cache_lock
+#endif /* CFG_INIT_RAM_LOCK_MIPS */