Merge with git://www.denx.de/git/u-boot.git

[u-boot] / cpu / mips / cache.S

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index aeb04b3790c30e478fddaed0b67a7ff8dfdc7cab..aad76e0afb8316bd262189616a5215b470c6bc47 100644 (file)
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -150,7 +150,7 @@ mips_cache_reset:
        sw      zero, 28(a0)
        addu    a0, 32
        bltu    a0, a1, 2b
-   
+
        /* Set invalid tag.
         */
 
@@ -250,16 +250,20 @@ dcache_disable:
 * RETURNS: N/A
 *
 */
+#if defined(CONFIG_PURPLE)
+# define       CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
+#else
+# define       CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
+#endif
        .globl  mips_cache_lock
        .ent    mips_cache_lock
 mips_cache_lock:
-       li      a1, K0BASE - CFG_DCACHE_SIZE
+       li      a1, K0BASE - CACHE_LOCK_SIZE
        addu    a0, a1
-       li      a2, CFG_DCACHE_SIZE
+       li      a2, CACHE_LOCK_SIZE
        li      a3, CFG_CACHELINE_SIZE
        move    a1, a2
        icacheop(a0,a1,a2,a3,0x1d)
 
        j       ra
        .end    mips_cache_lock
-