mpc83xx: clean up cache operations and unlock_ram_in_cache() functions

[u-boot] / cpu / mips / cache.S

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 89ada716c3adbe60b3ed912531fb9d23edfc4abc..ee5d411e4b6291f0b91b55f3af189208a7eb5dab 100644 (file)
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -23,7 +23,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/asm.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
@@ -41,7 +40,7 @@
  */
 #define MIPS_MAX_CACHE_SIZE    0x10000
 
-#define INDEX_BASE     KSEG0
+#define INDEX_BASE     CKSEG0
 
        .macro  cache_op op addr
        .set    push
@@ -219,7 +218,7 @@ NESTED(mips_cache_reset, 0, ra)
        /*
         * Now clear that much memory starting from zero.
         */
-       PTR_LI          a0, KSEG1
+       PTR_LI          a0, CKSEG1
        PTR_ADDU        a1, a0, v0
 2:     PTR_ADDIU       a0, 64
        f_fill64        a0, -64, zero
@@ -240,14 +239,16 @@ NESTED(mips_cache_reset, 0, ra)
         */
        move    a1, t2
        move    a2, t4
-       bal     mips_init_icache
+       PTR_LA  t7, mips_init_icache
+       jalr    t7
 
        /*
         * then initialize D-cache.
         */
        move    a1, t3
        move    a2, t5
-       bal     mips_init_dcache
+       PTR_LA  t7, mips_init_dcache
+       jalr    t7
 
        jr      RA
        END(mips_cache_reset)
@@ -282,9 +283,25 @@ LEAF(dcache_disable)
        and     t0, t0, t1
        ori     t0, t0, CONF_CM_UNCACHED
        mtc0    t0, CP0_CONFIG
-       j       ra
+       jr      ra
        END(dcache_disable)
 
+/*******************************************************************************
+*
+* dcache_enable - enable cache
+*
+* RETURNS: N/A
+*
+*/
+LEAF(dcache_enable)
+       mfc0    t0, CP0_CONFIG
+       ori     t0, CONF_CM_CMASK
+       xori    t0, CONF_CM_CMASK
+       ori     t0, CONF_CM_CACHABLE_NONCOHERENT
+       mtc0    t0, CP0_CONFIG
+       jr      ra
+       END(dcache_enable)
+
 #ifdef CFG_INIT_RAM_LOCK_MIPS
 /*******************************************************************************
 *
@@ -301,14 +318,14 @@ LEAF(dcache_disable)
        .globl  mips_cache_lock
        .ent    mips_cache_lock
 mips_cache_lock:
-       li      a1, K0BASE - CACHE_LOCK_SIZE
+       li      a1, CKSEG0 - CACHE_LOCK_SIZE
        addu    a0, a1
        li      a2, CACHE_LOCK_SIZE
        li      a3, CFG_CACHELINE_SIZE
        move    a1, a2
        icacheop(a0,a1,a2,a3,0x1d)
 
-       j       ra
+       jr      ra
 
        .end    mips_cache_lock
 #endif /* CFG_INIT_RAM_LOCK_MIPS */