ppc4xx: Add function to check and dynamically change PCI sync clock

[u-boot] / cpu / mips / cache.S

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 1b0efc34a7c3da52d8feb8fac2f90695e59cedfd..ff4f11cf7878e9718bb372b1a4dc3c39c0491f67 100644 (file)
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -23,7 +23,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/asm.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
@@ -41,7 +40,7 @@
  */
 #define MIPS_MAX_CACHE_SIZE    0x10000
 
-#define INDEX_BASE     KSEG0
+#define INDEX_BASE     CKSEG0
 
        .macro  cache_op op addr
        .set    push
@@ -209,9 +208,9 @@ LEAF(mips_init_dcache)
 */
 NESTED(mips_cache_reset, 0, ra)
        move    RA, ra
-       li      t2, CFG_ICACHE_SIZE
-       li      t3, CFG_DCACHE_SIZE
-       li      t4, CFG_CACHELINE_SIZE
+       li      t2, CONFIG_SYS_ICACHE_SIZE
+       li      t3, CONFIG_SYS_DCACHE_SIZE
+       li      t4, CONFIG_SYS_CACHELINE_SIZE
        move    t5, t4
 
        li      v0, MIPS_MAX_CACHE_SIZE
@@ -219,7 +218,7 @@ NESTED(mips_cache_reset, 0, ra)
        /*
         * Now clear that much memory starting from zero.
         */
-       PTR_LI          a0, KSEG1
+       PTR_LI          a0, CKSEG1
        PTR_ADDU        a1, a0, v0
 2:     PTR_ADDIU       a0, 64
        f_fill64        a0, -64, zero
@@ -303,7 +302,7 @@ LEAF(dcache_enable)
        jr      ra
        END(dcache_enable)
 
-#ifdef CFG_INIT_RAM_LOCK_MIPS
+#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
 /*******************************************************************************
 *
 * mips_cache_lock - lock RAM area pointed to by a0 in cache.
@@ -312,21 +311,21 @@ LEAF(dcache_enable)
 *
 */
 #if defined(CONFIG_PURPLE)
-# define       CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
+# define       CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
 #else
-# define       CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
+# define       CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
 #endif
        .globl  mips_cache_lock
        .ent    mips_cache_lock
 mips_cache_lock:
-       li      a1, K0BASE - CACHE_LOCK_SIZE
+       li      a1, CKSEG0 - CACHE_LOCK_SIZE
        addu    a0, a1
        li      a2, CACHE_LOCK_SIZE
-       li      a3, CFG_CACHELINE_SIZE
+       li      a3, CONFIG_SYS_CACHELINE_SIZE
        move    a1, a2
        icacheop(a0,a1,a2,a3,0x1d)
 
        jr      ra
 
        .end    mips_cache_lock
-#endif /* CFG_INIT_RAM_LOCK_MIPS */
+#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */