[MIPS] Implement flush_cache()

[u-boot] / cpu / mips / cpu.c

diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index e9676c1288687991c1fd5d680936ad96a1996729..de70c4d6142a430e9fce4d83ce0453abbcded218 100644 (file)
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -24,12 +24,24 @@
 #include <common.h>
 #include <command.h>
 #include <asm/inca-ip.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+
+#define cache_op(op,addr)                                              \
+       __asm__ __volatile__(                                           \
+       "       .set    push                                    \n"     \
+       "       .set    noreorder                               \n"     \
+       "       .set    mips3\n\t                               \n"     \
+       "       cache   %0, %1                                  \n"     \
+       "       .set    pop                                     \n"     \
+       :                                                               \
+       : "i" (op), "R" (*(unsigned char *)(addr)))
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 #if defined(CONFIG_INCA_IP)
        *INCA_IP_WDT_RST_REQ = 0x3f;
-#elif defined(CONFIG_PURPLE)
+#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
        void (*f)(void) = (void *) 0xbfc00000;
 
        f();
@@ -38,8 +50,27 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        return 0;
 }
 
-void flush_cache (ulong start_addr, ulong size)
+void flush_cache(ulong start_addr, ulong size)
 {
+       unsigned long lsize = CFG_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
+       while (1) {
+               cache_op(Hit_Writeback_Inv_D, start_addr);
+               cache_op(Hit_Invalidate_I, start_addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
 }
 
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
+       write_32bit_cp0_register(CP0_ENTRYLO0, low0);
+       write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
+       write_32bit_cp0_register(CP0_ENTRYLO1, low1);
+       write_32bit_cp0_register(CP0_ENTRYHI, hi);
+       write_32bit_cp0_register(CP0_INDEX, index);
+       tlb_write_indexed();
+}