Merge branch 'next' of git://git.denx.de/u-boot-avr32

[u-boot] / cpu / mpc8260 / pci.c

diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index cb0c79bf2082937dabeb48e811b0f667399b15ec..82303644b2be6df407b296992f3c251f90e839eb 100644 (file)
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (c) 2005 MontaVista Software, Inc.   
+ * Copyright (c) 2005 MontaVista Software, Inc.
  * Vitaly Bordug <vbordug@ru.mvista.com>
  * Added support for PCI bridge on MPC8272ADS
  *
@@ -33,6 +33,15 @@
 #include <mpc8260.h>
 #include <asm/m8260_pci.h>
 #include <asm/io.h>
+#ifdef CONFIG_OF_LIBFDT
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /*
  *   Local->PCI map (from CPU)                            controlled by
  *   MPC826x master window
@@ -234,9 +243,6 @@ static inline void pci_outl (u32 addr, u32 data)
 
 void pci_mpc8250_init (struct pci_controller *hose)
 {
-#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
-       DECLARE_GLOBAL_DATA_PTR;
-#endif
        u16 tempShort;
 
        volatile immap_t *immap = (immap_t *) CFG_IMMR;
@@ -253,26 +259,27 @@ void pci_mpc8250_init (struct pci_controller *hose)
                (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
                | SIUMCR_LBPC01;
 #elif defined CONFIG_MPC8272
-       immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & 
-                                  ~SIUMCR_BBD &
-                                  ~SIUMCR_ESE &
-                                  ~SIUMCR_PBSE &
-                                  ~SIUMCR_CDIS &
-                                  ~SIUMCR_DPPC11 &
-                                  ~SIUMCR_L2CPC11 &
-                                  ~SIUMCR_LBPC11 &
-                                  ~SIUMCR_APPC11 &
-                                  ~SIUMCR_CS10PC11 &
-                                  ~SIUMCR_BCTLC11 &
-                                  ~SIUMCR_MMR11)
-                                  | SIUMCR_DPPC11
-                                  | SIUMCR_L2CPC01
-                                  | SIUMCR_LBPC00
-                                  | SIUMCR_APPC10
-                                  | SIUMCR_CS10PC00
-                                  | SIUMCR_BCTLC00
-                                  | SIUMCR_MMR11;
-
+       immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+                                 ~SIUMCR_BBD &
+                                 ~SIUMCR_ESE &
+                                 ~SIUMCR_PBSE &
+                                 ~SIUMCR_CDIS &
+                                 ~SIUMCR_DPPC11 &
+                                 ~SIUMCR_L2CPC11 &
+                                 ~SIUMCR_LBPC11 &
+                                 ~SIUMCR_APPC11 &
+                                 ~SIUMCR_CS10PC11 &
+                                 ~SIUMCR_BCTLC11 &
+                                 ~SIUMCR_MMR11)
+                                 | SIUMCR_DPPC11
+                                 | SIUMCR_L2CPC01
+                                 | SIUMCR_LBPC00
+                                 | SIUMCR_APPC10
+                                 | SIUMCR_CS10PC00
+                                 | SIUMCR_BCTLC00
+                                 | SIUMCR_MMR11;
+#elif defined(CONFIG_TQM8272)
+/* nothing to do for this Board here */
 #else
        /*
         * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
@@ -399,7 +406,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
        hose->last_busno = 0xff;
 
        /* System memory space */
-#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
        pci_set_region (hose->regions + 0,
                        PCI_SLV_MEM_BUS,
                        PCI_SLV_MEM_LOCAL,
@@ -412,7 +419,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
 #endif
 
        /* PCI memory space */
-#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
        pci_set_region (hose->regions + 1,
                        PCI_MSTR_MEMIO_BUS,
                        PCI_MSTR_MEMIO_LOCAL,
@@ -446,4 +453,12 @@ void pci_mpc8250_init (struct pci_controller *hose)
        immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
 }
 
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+       do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
+               "clock-frequency", gd->pci_clk, 1);
+}
+#endif
+
 #endif /* CONFIG_PCI */