Merge commit 'wd/master'

[u-boot] / cpu / mpc83xx / spd_sdram.c

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index ee2d0385e457b6bcc8b720024aba63e3b8ef5096..76f2474491a7b36441d5608e8bff64b95f62996b 100644 (file)
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2006 Freescale Semiconductor, Inc.
+ * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -34,10 +34,13 @@
 #include <asm/mmu.h>
 #include <spd_sdram.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void board_add_ram_info(int use_default)
 {
        volatile immap_t *immap = (immap_t *) CFG_IMMR;
        volatile ddr83xx_t *ddr = &immap->ddr;
+       char buf[32];
 
        printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
                           >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
@@ -48,9 +51,11 @@ void board_add_ram_info(int use_default)
                puts(", 64-bit");
 
        if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
-               puts(", ECC on)");
+               puts(", ECC on");
        else
-               puts(", ECC off)");
+               puts(", ECC off");
+
+       printf(", %s MHz)", strmhz(buf, gd->mem_clk));
 
 #if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
        puts("\nSDRAM: ");
@@ -60,8 +65,6 @@ void board_add_ram_info(int use_default)
 
 #ifdef CONFIG_SPD_EEPROM
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 extern void dma_init(void);
 extern uint dma_check(void);
@@ -78,12 +81,12 @@ extern int dma_xfer(void *dest, uint count, void *src);
 int
 picos_to_clk(int picos)
 {
-       unsigned int ddr_bus_clk;
+       unsigned int mem_bus_clk;
        int clks;
 
-       ddr_bus_clk = gd->ddr_clk >> 1;
-       clks = picos / (1000000000 / (ddr_bus_clk / 1000));
-       if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
+       mem_bus_clk = gd->mem_clk >> 1;
+       clks = picos / (1000000000 / (mem_bus_clk / 1000));
+       if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
                clks++;
 
        return clks;
@@ -198,6 +201,7 @@ long int spd_sdram()
        if(spd.mem_type == SPD_MEMTYPE_DDR2) {
                immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
        }
+       udelay(50000);
 #endif
 
        /*
@@ -312,7 +316,7 @@ long int spd_sdram()
 
        debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
 
-       ddrc_clk = gd->ddr_clk / 1000000;
+       ddrc_clk = gd->mem_clk / 1000000;
        effective_data_rate = 0;
 
        if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
@@ -506,7 +510,7 @@ long int spd_sdram()
        ddr->timing_cfg_1 =
            (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |    /* PRETOACT */
             ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
-            (trcd_clk << 20 ) |                                /* ACTTORW */
+            (trcd_clk << 20 ) |                                /* ACTTORW */
             (caslat_ctrl << 16 ) |                             /* CASLAT */
             (trfc_low << 12 ) |                                /* REFEC */
             ((twr_clk & 0x07) << 8) |                          /* WRRREC */
@@ -573,10 +577,10 @@ long int spd_sdram()
         */
        cpo = 0;
        if (spd.mem_type == SPD_MEMTYPE_DDR2) {
-               if (effective_data_rate == 266 || effective_data_rate == 333) {
+               if (effective_data_rate == 266) {
+                       cpo = 0x4;              /* READ_LAT + 1/2 */
+               } else if (effective_data_rate == 333 || effective_data_rate == 400) {
                        cpo = 0x7;              /* READ_LAT + 5/4 */
-               } else if (effective_data_rate == 400) {
-                       cpo = 0x9;              /* READ_LAT + 7/4 */
                } else {
                        /* Automatic calibration */
                        cpo = 0x1f;
@@ -597,7 +601,7 @@ long int spd_sdram()
        debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
 
        /* Check DIMM data bus width */
-       if (spd.dataw_lsb == 0x20) {
+       if (spd.dataw_lsb < 64) {
                if (spd.mem_type == SPD_MEMTYPE_DDR)
                        burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
                else
@@ -705,9 +709,11 @@ long int spd_sdram()
         * SDRAM Cfg 2
         */
        odt_cfg = 0;
+#ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
        if (odt_rd_cfg | odt_wr_cfg) {
                odt_cfg = 0x2;          /* ODT to IOs during reads */
        }
+#endif
        if (spd.mem_type == SPD_MEMTYPE_DDR2) {
                ddr->sdram_cfg2 = (0
                            | (0 << 26) /* True DQS */
@@ -757,7 +763,7 @@ long int spd_sdram()
                sdram_cfg |= SDRAM_CFG_RD_EN;
 
        /* The DIMM is 32bit width */
-       if (spd.dataw_lsb == 0x20) {
+       if (spd.dataw_lsb < 64) {
                if (spd.mem_type == SPD_MEMTYPE_DDR)
                        sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
                if (spd.mem_type == SPD_MEMTYPE_DDR2)