86xx: Report which "bank" of NOR flash we are booting from on MPC8641HPCN

[u-boot] / cpu / mpc85xx / cpu.c

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 943602f923ee91d109949e84d7546d33be426764..28c6119d3dea9c03abbc7a74ceb4e22ad9d04fa7 100644 (file)
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -31,6 +31,7 @@
 #include <command.h>
 #include <tsec.h>
 #include <netdev.h>
+#include <fsl_esdhc.h>
 #include <asm/cache.h>
 #include <asm/io.h>
 
@@ -39,6 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;
 struct cpu_type cpu_type_list [] = {
        CPU_TYPE_ENTRY(8533, 8533),
        CPU_TYPE_ENTRY(8533, 8533_E),
+       CPU_TYPE_ENTRY(8535, 8535),
+       CPU_TYPE_ENTRY(8535, 8535_E),
        CPU_TYPE_ENTRY(8536, 8536),
        CPU_TYPE_ENTRY(8536, 8536_E),
        CPU_TYPE_ENTRY(8540, 8540),
@@ -60,8 +63,12 @@ struct cpu_type cpu_type_list [] = {
        CPU_TYPE_ENTRY(8567, 8567_E),
        CPU_TYPE_ENTRY(8568, 8568),
        CPU_TYPE_ENTRY(8568, 8568_E),
+       CPU_TYPE_ENTRY(8569, 8569),
+       CPU_TYPE_ENTRY(8569, 8569_E),
        CPU_TYPE_ENTRY(8572, 8572),
        CPU_TYPE_ENTRY(8572, 8572_E),
+       CPU_TYPE_ENTRY(P2020, P2020),
+       CPU_TYPE_ENTRY(P2020, P2020_E),
 };
 
 struct cpu_type *identify_cpu(u32 ver)
@@ -77,8 +84,6 @@ struct cpu_type *identify_cpu(u32 ver)
 int checkcpu (void)
 {
        sys_info_t sysinfo;
-       uint lcrr;              /* local bus clock ratio register */
-       uint clkdiv;            /* clock divider portion of lcrr */
        uint pvr, svr;
        uint fam;
        uint ver;
@@ -92,6 +97,7 @@ int checkcpu (void)
 #else
        u32 ddr_ratio = 0;
 #endif
+       int i;
 
        svr = get_svr();
        ver = SVR_SOC_VER(svr);
@@ -143,9 +149,14 @@ int checkcpu (void)
 
        get_sys_info(&sysinfo);
 
-       puts("Clock Configuration:\n");
-       printf("       CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
-       printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
+       puts("Clock Configuration:");
+       for (i = 0; i < CONFIG_NUM_CPUS; i++) {
+               if (!(i & 3))
+                       printf ("\n       ");
+               printf("CPU%d:%-4s MHz, ",
+                               i,strmhz(buf1, sysinfo.freqProcessor[i]));
+       }
+       printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
 
        switch (ddr_ratio) {
        case 0x0:
@@ -165,35 +176,20 @@ int checkcpu (void)
                break;
        }
 
-#if defined(CONFIG_SYS_LBC_LCRR)
-       lcrr = CONFIG_SYS_LBC_LCRR;
-#else
-       {
-           volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
-           lcrr = lbc->lcrr;
-       }
-#endif
-       clkdiv = lcrr & 0x0f;
-       if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
-    defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
-               /*
-                * Yes, the entire PQ38 family use the same
-                * bit-representation for twice the clock divider values.
-                */
-                clkdiv *= 2;
-#endif
-               printf("LBC:%-4s MHz\n",
-                      strmhz(buf1, sysinfo.freqSystemBus / clkdiv));
-       } else {
-               printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
-       }
+       if (sysinfo.freqLocalBus > LCRR_CLKDIV)
+               printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+       else
+               printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
+                      sysinfo.freqLocalBus);
 
 #ifdef CONFIG_CPM2
        printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
 #endif
 
+#ifdef CONFIG_QE
+       printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
+#endif
+
        puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 
        return 0;
@@ -268,50 +264,6 @@ reset_85xx_watchdog(void)
 }
 #endif /* CONFIG_WATCHDOG */
 
-#if defined(CONFIG_DDR_ECC)
-void dma_init(void) {
-       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
-
-       dma->satr0 = 0x02c40000;
-       dma->datr0 = 0x02c40000;
-       dma->sr0 = 0xfffffff; /* clear any errors */
-       asm("sync; isync; msync");
-       return;
-}
-
-uint dma_check(void) {
-       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
-       volatile uint status = dma->sr0;
-
-       /* While the channel is busy, spin */
-       while((status & 4) == 4) {
-               status = dma->sr0;
-       }
-
-       /* clear MR0[CS] channel start bit */
-       dma->mr0 &= 0x00000001;
-       asm("sync;isync;msync");
-
-       if (status != 0) {
-               printf ("DMA Error: status = %x\n", status);
-       }
-       return status;
-}
-
-int dma_xfer(void *dest, uint count, void *src) {
-       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
-
-       dma->dar0 = (uint) dest;
-       dma->sar0 = (uint) src;
-       dma->bcr0 = count;
-       dma->mr0 = 0xf000004;
-       asm("sync;isync;msync");
-       dma->mr0 = 0xf000005;
-       asm("sync;isync;msync");
-       return dma_check();
-}
-#endif
-
 /*
  * Configures a UPM. The function requires the respective MxMR to be set
  * before calling this function. "size" is the number or entries, not a sizeof.
@@ -387,26 +339,27 @@ int cpu_eth_init(bd_t *bis)
 #if defined(CONFIG_ETHER_ON_FCC)
        fec_initialize(bis);
 #endif
-#if defined(CONFIG_UEC_ETH1)
-       uec_initialize(0);
-#endif
-#if defined(CONFIG_UEC_ETH2)
-       uec_initialize(1);
-#endif
-#if defined(CONFIG_UEC_ETH3)
-       uec_initialize(2);
-#endif
-#if defined(CONFIG_UEC_ETH4)
-       uec_initialize(3);
-#endif
-#if defined(CONFIG_UEC_ETH5)
-       uec_initialize(4);
-#endif
-#if defined(CONFIG_UEC_ETH6)
-       uec_initialize(5);
+
+#if defined(CONFIG_UEC_ETH)
+       uec_standard_init(bis);
 #endif
+
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
        tsec_standard_init(bis);
 #endif
+
+       return 0;
+}
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+       return fsl_esdhc_mmc_init(bis);
+#else
        return 0;
+#endif
 }