85xx if NUM_CPUS>1, print cpu number

[u-boot] / cpu / mpc85xx / cpu.c

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index c64bf1050be7384043fbf1a2b5ea8a0dd70e2f2f..9c4f2145025f8d2d12004006075a40e0775b5fb4 100644 (file)
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -25,16 +25,21 @@
  * MA 02111-1307 USA
  */
 
+#include <config.h>
 #include <common.h>
 #include <watchdog.h>
 #include <command.h>
+#include <tsec.h>
 #include <asm/cache.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 struct cpu_type cpu_type_list [] = {
        CPU_TYPE_ENTRY(8533, 8533),
        CPU_TYPE_ENTRY(8533, 8533_E),
+       CPU_TYPE_ENTRY(8536, 8536),
+       CPU_TYPE_ENTRY(8536, 8536_E),
        CPU_TYPE_ENTRY(8540, 8540),
        CPU_TYPE_ENTRY(8541, 8541),
        CPU_TYPE_ENTRY(8541, 8541_E),
@@ -58,7 +63,7 @@ struct cpu_type cpu_type_list [] = {
        CPU_TYPE_ENTRY(8572, 8572_E),
 };
 
-struct cpu_type *identify_cpu(uint ver)
+struct cpu_type *identify_cpu(u32 ver)
 {
        int i;
        for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
@@ -79,8 +84,9 @@ int checkcpu (void)
        uint major, minor;
        struct cpu_type *cpu;
 #ifdef CONFIG_DDR_CLK_FREQ
-       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-       u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+               >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 #else
        u32 ddr_ratio = 0;
 #endif
@@ -88,15 +94,23 @@ int checkcpu (void)
        svr = get_svr();
        ver = SVR_SOC_VER(svr);
        major = SVR_MAJ(svr);
+#ifdef CONFIG_MPC8536
+       major &= 0x7; /* the msb of this nibble is a mfg code */
+#endif
        minor = SVR_MIN(svr);
 
+#if (CONFIG_NUM_CPUS > 1)
+       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+       printf("CPU%d:  ", pic->whoami);
+#else
        puts("CPU:   ");
+#endif
 
        cpu = identify_cpu(ver);
        if (cpu) {
                puts(cpu->name);
 
-               if (svr & 0x80000)
+               if (IS_E_PROCESSOR(svr))
                        puts("E");
        } else {
                puts("Unknown");
@@ -142,18 +156,19 @@ int checkcpu (void)
                break;
        }
 
-#if defined(CFG_LBC_LCRR)
-       lcrr = CFG_LBC_LCRR;
+#if defined(CONFIG_SYS_LBC_LCRR)
+       lcrr = CONFIG_SYS_LBC_LCRR;
 #else
        {
-           volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+           volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
            lcrr = lbc->lcrr;
        }
 #endif
        clkdiv = lcrr & 0x0f;
        if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
+#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
+    defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
                /*
                 * Yes, the entire PQ38 family use the same
                 * bit-representation for twice the clock divider values.
@@ -190,7 +205,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
        if (ver & 1){
        /* e500 v2 core has reset control register */
                volatile unsigned int * rstcr;
-               rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
+               rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
                *rstcr = 0x2;           /* HRESET_REQ */
                udelay(100);
        }
@@ -246,7 +261,7 @@ reset_85xx_watchdog(void)
 
 #if defined(CONFIG_DDR_ECC)
 void dma_init(void) {
-       volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
+       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
 
        dma->satr0 = 0x02c40000;
        dma->datr0 = 0x02c40000;
@@ -256,7 +271,7 @@ void dma_init(void) {
 }
 
 uint dma_check(void) {
-       volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
+       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
        volatile uint status = dma->sr0;
 
        /* While the channel is busy, spin */
@@ -275,7 +290,7 @@ uint dma_check(void) {
 }
 
 int dma_xfer(void *dest, uint count, void *src) {
-       volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
+       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
 
        dma->dar0 = (uint) dest;
        dma->sar0 = (uint) src;
@@ -287,3 +302,82 @@ int dma_xfer(void *dest, uint count, void *src) {
        return dma_check();
 }
 #endif
+
+/*
+ * Configures a UPM. The function requires the respective MxMR to be set
+ * before calling this function. "size" is the number or entries, not a sizeof.
+ */
+void upmconfig (uint upm, uint * table, uint size)
+{
+       int i, mdr, mad, old_mad = 0;
+       volatile u32 *mxmr;
+       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+       volatile u32 *brp,*orp;
+       volatile u8* dummy = NULL;
+       int upmmask;
+
+       switch (upm) {
+       case UPMA:
+               mxmr = &lbc->mamr;
+               upmmask = BR_MS_UPMA;
+               break;
+       case UPMB:
+               mxmr = &lbc->mbmr;
+               upmmask = BR_MS_UPMB;
+               break;
+       case UPMC:
+               mxmr = &lbc->mcmr;
+               upmmask = BR_MS_UPMC;
+               break;
+       default:
+               printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
+               hang();
+       }
+
+       /* Find the address for the dummy write transaction */
+       for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
+                i++, brp += 2, orp += 2) {
+
+               /* Look for a valid BR with selected UPM */
+               if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
+                       dummy = (volatile u8*)(in_be32(brp) & BR_BA);
+                       break;
+               }
+       }
+
+       if (i == 8) {
+               printf("Error: %s() could not find matching BR\n", __FUNCTION__);
+               hang();
+       }
+
+       for (i = 0; i < size; i++) {
+               /* 1 */
+               out_be32(mxmr,  (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
+               /* 2 */
+               out_be32(&lbc->mdr, table[i]);
+               /* 3 */
+               mdr = in_be32(&lbc->mdr);
+               /* 4 */
+               *(volatile u8 *)dummy = 0;
+               /* 5 */
+               do {
+                       mad = in_be32(mxmr) & MxMR_MAD_MSK;
+               } while (mad <= old_mad && !(!mad && i == (size-1)));
+               old_mad = mad;
+       }
+       out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
+}
+
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC)
+       tsec_standard_init(bis);
+#endif
+
+       return 0;
+}