ppc/85xx: Clean up do_reset

[u-boot] / cpu / mpc85xx / cpu.c

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 8b3810f5b00f64705dcd1688b49a4341b9271308..bdd9ee4c83348ec8ba018373d7c529bddb36e667 100644 (file)
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -153,27 +153,15 @@ int checkcpu (void)
 
 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 {
-       uint pvr;
-       uint ver;
+/* Everything after the first generation of PQ3 parts has RSTCR */
+#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+    defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
        unsigned long val, msr;
 
-       pvr = get_pvr();
-       ver = PVR_VER(pvr);
-
-       if (ver & 1){
-       /* e500 v2 core has reset control register */
-               volatile unsigned int * rstcr;
-               rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
-               *rstcr = 0x2;           /* HRESET_REQ */
-               udelay(100);
-       }
-
        /*
-        * Fallthrough if the code above failed
         * Initiate hard reset in debug control register DBCR0
-        * Make sure MSR[DE] = 1
+        * Make sure MSR[DE] = 1.  This only resets the core.
         */
-
        msr = mfmsr ();
        msr |= MSR_DE;
        mtmsr (msr);
@@ -181,6 +169,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
        val = mfspr(DBCR0);
        val |= 0x70000000;
        mtspr(DBCR0,val);
+#else
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       out_be32(&gur->rstcr, 0x2);     /* HRESET_REQ */
+       udelay(100);
+#endif
 
        return 1;
 }