Make Freescale local bus registers available for both 83xx and 85xx.

[u-boot] / cpu / mpc85xx / cpu.c

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 7976caca67eb572188793289e5cc267c0854a260..c78068786650582d0bffeb33d8cb246e7e20e5f1 100644 (file)
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -83,9 +83,11 @@ int checkcpu (void)
        uint ver;
        uint major, minor;
        struct cpu_type *cpu;
+       char buf1[32], buf2[32];
 #ifdef CONFIG_DDR_CLK_FREQ
-       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-       u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+               >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 #else
        u32 ddr_ratio = 0;
 #endif
@@ -98,7 +100,12 @@ int checkcpu (void)
 #endif
        minor = SVR_MIN(svr);
 
+#if (CONFIG_NUM_CPUS > 1)
+       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+       printf("CPU%d:  ", pic->whoami);
+#else
        puts("CPU:   ");
+#endif
 
        cpu = identify_cpu(ver);
        if (cpu) {
@@ -127,34 +134,41 @@ int checkcpu (void)
            puts("Unknown");
            break;
        }
+
+       if (PVR_MEM(pvr) == 0x03)
+               puts("MC");
+
        printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 
        get_sys_info(&sysinfo);
 
        puts("Clock Configuration:\n");
-       printf("       CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
-       printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
+       printf("       CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
+       printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
 
        switch (ddr_ratio) {
        case 0x0:
-               printf("       DDR:%4lu MHz (%lu MT/s data rate), ",
-               DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
+               printf("       DDR:%-4s MHz (%s MT/s data rate), ",
+                       strmhz(buf1, sysinfo.freqDDRBus/2),
+                       strmhz(buf2, sysinfo.freqDDRBus));
                break;
        case 0x7:
-               printf("       DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
-               DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
+               printf("       DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
+                       strmhz(buf1, sysinfo.freqDDRBus/2),
+                       strmhz(buf2, sysinfo.freqDDRBus));
                break;
        default:
-               printf("       DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
-               DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
+               printf("       DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
+                       strmhz(buf1, sysinfo.freqDDRBus/2),
+                       strmhz(buf2, sysinfo.freqDDRBus));
                break;
        }
 
-#if defined(CFG_LBC_LCRR)
-       lcrr = CFG_LBC_LCRR;
+#if defined(CONFIG_SYS_LBC_LCRR)
+       lcrr = CONFIG_SYS_LBC_LCRR;
 #else
        {
-           volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+           volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
            lcrr = lbc->lcrr;
        }
@@ -169,14 +183,14 @@ int checkcpu (void)
                 */
                 clkdiv *= 2;
 #endif
-               printf("LBC:%4lu MHz\n",
-                      DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
+               printf("LBC:%-4s MHz\n",
+                      strmhz(buf1, sysinfo.freqSystemBus / clkdiv));
        } else {
                printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
        }
 
 #ifdef CONFIG_CPM2
-       printf("CPM:   %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+       printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
 #endif
 
        puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
@@ -199,7 +213,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
        if (ver & 1){
        /* e500 v2 core has reset control register */
                volatile unsigned int * rstcr;
-               rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
+               rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
                *rstcr = 0x2;           /* HRESET_REQ */
                udelay(100);
        }
@@ -255,7 +269,7 @@ reset_85xx_watchdog(void)
 
 #if defined(CONFIG_DDR_ECC)
 void dma_init(void) {
-       volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
+       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
 
        dma->satr0 = 0x02c40000;
        dma->datr0 = 0x02c40000;
@@ -265,7 +279,7 @@ void dma_init(void) {
 }
 
 uint dma_check(void) {
-       volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
+       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
        volatile uint status = dma->sr0;
 
        /* While the channel is busy, spin */
@@ -284,7 +298,7 @@ uint dma_check(void) {
 }
 
 int dma_xfer(void *dest, uint count, void *src) {
-       volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
+       volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
 
        dma->dar0 = (uint) dest;
        dma->sar0 = (uint) src;
@@ -298,15 +312,14 @@ int dma_xfer(void *dest, uint count, void *src) {
 #endif
 
 /*
- * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
- * are hardcoded as "1"."size" is the number or entries, not a sizeof.
+ * Configures a UPM. The function requires the respective MxMR to be set
+ * before calling this function. "size" is the number or entries, not a sizeof.
  */
 void upmconfig (uint upm, uint * table, uint size)
 {
        int i, mdr, mad, old_mad = 0;
        volatile u32 *mxmr;
-       volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-       int loopval = 0x00004440;
+       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
        volatile u32 *brp,*orp;
        volatile u8* dummy = NULL;
        int upmmask;
@@ -334,8 +347,8 @@ void upmconfig (uint upm, uint * table, uint size)
                 i++, brp += 2, orp += 2) {
 
                /* Look for a valid BR with selected UPM */
-               if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
-                       dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
+               if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
+                       dummy = (volatile u8*)(in_be32(brp) & BR_BA);
                        break;
                }
        }
@@ -347,7 +360,7 @@ void upmconfig (uint upm, uint * table, uint size)
 
        for (i = 0; i < size; i++) {
                /* 1 */
-               out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */
+               out_be32(mxmr,  (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
                /* 2 */
                out_be32(&lbc->mdr, table[i]);
                /* 3 */
@@ -356,11 +369,11 @@ void upmconfig (uint upm, uint * table, uint size)
                *(volatile u8 *)dummy = 0;
                /* 5 */
                do {
-                       mad = in_be32(mxmr) & 0x3f;
+                       mad = in_be32(mxmr) & MxMR_MAD_MSK;
                } while (mad <= old_mad && !(!mad && i == (size-1)));
                old_mad = mad;
        }
-       out_be32(mxmr, loopval); /* OP_NORMAL */
+       out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
 }