OMAP3: Fix SDRC init

[u-boot] / cpu / mpc85xx / cpu_init.c

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 48a82eda6d8006432db98527b47c05058f8e1795..0041a60df967c0c51ee97c004a038a50e6ad9238 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -136,6 +136,20 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
  * initialize a bunch of registers
  */
 
+#ifdef CONFIG_FSL_CORENET
+static void corenet_tb_init(void)
+{
+       volatile ccsr_rcpm_t *rcpm =
+               (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+       volatile ccsr_pic_t *pic =
+               (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+       u32 whoami = in_be32(&pic->whoami);
+
+       /* Enable the timebase register for this core */
+       out_be32(&rcpm->ctbenrl, (1 << whoami));
+}
+#endif
+
 void cpu_init_f (void)
 {
        volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@@ -229,6 +243,9 @@ void cpu_init_f (void)
 #if defined(CONFIG_FSL_DMA)
        dma_init();
 #endif
+#ifdef CONFIG_FSL_CORENET
+       corenet_tb_init();
+#endif
 }
 
 
@@ -336,15 +353,18 @@ int cpu_init_r(void)
        u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 
        /* invalidate the L2 cache */
-       mtspr(SPRN_L2CSR0, L2CSR0_L2FI);
-       while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI)
+       mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
+       while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
                ;
 
        /* enable the cache */
        mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
 
-       if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E)
+       if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
+               while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
+                       ;
                printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
+       }
 #else
        puts("disabled\n");
 #endif
@@ -364,5 +384,16 @@ extern void setup_ivors(void);
 
 void arch_preboot_os(void)
 {
+       u32 msr;
+
+       /*
+        * We are changing interrupt offsets and are about to boot the OS so
+        * we need to make sure we disable all async interrupts. EE is already
+        * disabled by the time we get called.
+        */
+       msr = mfmsr();
+       msr &= ~(MSR_ME|MSR_CE|MSR_DE);
+       mtmsr(msr);
+
        setup_ivors();
 }