]> git.sur5r.net Git - u-boot/blobdiff - cpu/mpc85xx/cpu_init.c
Merge git://www.denx.de/git/u-boot into merge
[u-boot] / cpu / mpc85xx / cpu_init.c
index c7fe130ee0eee75217f98880dd00aa54ba6afc84..7b9961013c054a74881f43a51e79f25efd0d9697 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_QE
+extern qe_iop_conf_t qe_iop_conf_tab[];
+extern void qe_config_iopin(u8 port, u8 pin, int dir,
+                               int open_drain, int assign);
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+
+static void config_qe_ioports(void)
+{
+       u8      port, pin;
+       int     dir, open_drain, assign;
+       int     i;
+
+       for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
+               port            = qe_iop_conf_tab[i].port;
+               pin             = qe_iop_conf_tab[i].pin;
+               dir             = qe_iop_conf_tab[i].dir;
+               open_drain      = qe_iop_conf_tab[i].open_drain;
+               assign          = qe_iop_conf_tab[i].assign;
+               qe_config_iopin(port, pin, dir, open_drain, assign);
+       }
+}
+#endif
 
 #ifdef CONFIG_CPM2
 static void config_8560_ioports (volatile immap_t * immr)
@@ -181,6 +204,11 @@ void cpu_init_f (void)
 #if defined(CONFIG_CPM2)
        m8560_cpm_reset();
 #endif
+#ifdef CONFIG_QE
+       /* Config QE ioports */
+       config_qe_ioports();
+#endif
+
 }
 
 
@@ -262,6 +290,11 @@ int cpu_init_r(void)
 #else
        printf("L2 cache: disabled\n");
 #endif
+#ifdef CONFIG_QE
+       uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
+       qe_init(qe_base);
+       qe_reset();
+#endif
 
        return 0;
 }