/*
- * Copyright 2008 Freescale Semiconductor.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <ioports.h>
#include <lmb.h>
#include <asm/io.h>
+#include <asm/mmu.h>
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
int cpu_reset(int nr)
{
- volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
out_be32(&pic->pir, 1 << nr);
+ /* the dummy read works around an errata on early 85xx MP PICs */
(void)in_be32(&pic->pir);
out_be32(&pic->pir, 0x0);
return 1;
}
-#ifdef CFG_64BIT_STRTOUL
+#ifdef CONFIG_SYS_64BIT_STRTOUL
boot_addr = simple_strtoull(argv[0], NULL, 16);
#else
boot_addr = simple_strtoul(argv[0], NULL, 16);
return 0;
}
+u32 determine_mp_bootpg(void)
+{
+ /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
+ if ((u64)gd->ram_size > 0xfffff000)
+ return (0xfffff000);
+
+ return (gd->ram_size - 4096);
+}
+
ulong get_spin_addr(void)
{
extern ulong __secondary_start_page;
u32 up, cpu_up_mask, whoami;
u32 *table = (u32 *)get_spin_addr();
volatile u32 bpcr;
- volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
u32 devdisr;
int timeout = 10;
out_be32(&gur->devdisr, devdisr);
/* release the hounds */
- up = ((1 << CONFIG_NUM_CPUS) - 1);
+ up = ((1 << cpu_numcores()) - 1);
bpcr = in_be32(&ecm->eebpcr);
bpcr |= (up << 24);
out_be32(&ecm->eebpcr, bpcr);
/* wait for everyone */
while (timeout) {
int i;
- for (i = 0; i < CONFIG_NUM_CPUS; i++) {
+ for (i = 0; i < cpu_numcores(); i++) {
if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
cpu_up_mask |= (1 << i);
};
void cpu_mp_lmb_reserve(struct lmb *lmb)
{
- u32 bootpg;
-
- /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
- if ((u64)gd->ram_size > 0xfffff000)
- bootpg = 0xfffff000;
- else
- bootpg = gd->ram_size - 4096;
+ u32 bootpg = determine_mp_bootpg();
lmb_reserve(lmb, bootpg, 4096);
}
{
extern ulong __secondary_start_page;
ulong fixup = (ulong)&__secondary_start_page;
- u32 bootpg;
+ u32 bootpg = determine_mp_bootpg();
- /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
- if ((u64)gd->ram_size > 0xfffff000)
- bootpg = 0xfffff000;
- else
- bootpg = gd->ram_size - 4096;
+ /* look for the tlb covering the reset page, there better be one */
+ int i = find_tlb_idx((void *)0xfffff000, 1);
+
+ /* we found a match */
+ if (i != -1) {
+ /* map reset page to bootpg so we can copy code there */
+ disable_tlb(i);
+
+ set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */
+ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
- memcpy((void *)bootpg, (void *)fixup, 4096);
- flush_cache(bootpg, 4096);
+ memcpy((void *)0xfffff000, (void *)fixup, 4096);
+ flush_cache(0xfffff000, 4096);
- pq3_mp_up(bootpg);
+ disable_tlb(i);
+
+ /* setup reset page back to 1:1, we'll use HW boot translation
+ * to map this where we want
+ */
+ set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
+ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
+
+ pq3_mp_up(bootpg);
+ } else {
+ puts("WARNING: No reset page TLB. "
+ "Skipping secondary core setup\n");
+ }
}