ppc/p4080: CoreNet platfrom style CCSRBAR setting

[u-boot] / cpu / mpc85xx / mp.c

diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index 4e09c9c258bb5214f0a9399d02c420db869d889c..fa65bed083b2d64405a2d504219e4e45b8077975 100644 (file)
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,6 +25,7 @@
 #include <ioports.h>
 #include <lmb.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
 #include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -36,8 +37,9 @@ u32 get_my_id()
 
 int cpu_reset(int nr)
 {
-       volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
        out_be32(&pic->pir, 1 << nr);
+       /* the dummy read works around an errata on early 85xx MP PICs */
        (void)in_be32(&pic->pir);
        out_be32(&pic->pir, 0x0);
 
@@ -87,7 +89,7 @@ int cpu_release(int nr, int argc, char *argv[])
                return 1;
        }
 
-#ifdef CFG_64BIT_STRTOUL
+#ifdef CONFIG_SYS_64BIT_STRTOUL
        boot_addr = simple_strtoull(argv[0], NULL, 16);
 #else
        boot_addr = simple_strtoul(argv[0], NULL, 16);
@@ -112,6 +114,15 @@ int cpu_release(int nr, int argc, char *argv[])
        return 0;
 }
 
+u32 determine_mp_bootpg(void)
+{
+       /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
+       if ((u64)gd->ram_size > 0xfffff000)
+               return (0xfffff000);
+
+       return (gd->ram_size - 4096);
+}
+
 ulong get_spin_addr(void)
 {
        extern ulong __secondary_start_page;
@@ -129,9 +140,9 @@ static void pq3_mp_up(unsigned long bootpg)
        u32 up, cpu_up_mask, whoami;
        u32 *table = (u32 *)get_spin_addr();
        volatile u32 bpcr;
-       volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
-       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-       volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+       volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
        u32 devdisr;
        int timeout = 10;
 
@@ -147,7 +158,7 @@ static void pq3_mp_up(unsigned long bootpg)
        out_be32(&gur->devdisr, devdisr);
 
        /* release the hounds */
-       up = ((1 << CONFIG_NUM_CPUS) - 1);
+       up = ((1 << cpu_numcores()) - 1);
        bpcr = in_be32(&ecm->eebpcr);
        bpcr |= (up << 24);
        out_be32(&ecm->eebpcr, bpcr);
@@ -157,7 +168,7 @@ static void pq3_mp_up(unsigned long bootpg)
        /* wait for everyone */
        while (timeout) {
                int i;
-               for (i = 0; i < CONFIG_NUM_CPUS; i++) {
+               for (i = 0; i < cpu_numcores(); i++) {
                        if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
                                cpu_up_mask |= (1 << i);
                };
@@ -188,13 +199,7 @@ static void pq3_mp_up(unsigned long bootpg)
 
 void cpu_mp_lmb_reserve(struct lmb *lmb)
 {
-       u32 bootpg;
-
-       /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
-       if ((u64)gd->ram_size > 0xfffff000)
-               bootpg = 0xfffff000;
-       else
-               bootpg = gd->ram_size - 4096;
+       u32 bootpg = determine_mp_bootpg();
 
        lmb_reserve(lmb, bootpg, 4096);
 }
@@ -203,16 +208,35 @@ void setup_mp(void)
 {
        extern ulong __secondary_start_page;
        ulong fixup = (ulong)&__secondary_start_page;
-       u32 bootpg;
+       u32 bootpg = determine_mp_bootpg();
 
-       /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
-       if ((u64)gd->ram_size > 0xfffff000)
-               bootpg = 0xfffff000;
-       else
-               bootpg = gd->ram_size - 4096;
+       /* look for the tlb covering the reset page, there better be one */
+       int i = find_tlb_idx((void *)0xfffff000, 1);
+
+       /* we found a match */
+       if (i != -1) {
+               /* map reset page to bootpg so we can copy code there */
+               disable_tlb(i);
+       
+               set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */
+                       0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
 
-       memcpy((void *)bootpg, (void *)fixup, 4096);
-       flush_cache(bootpg, 4096);
+               memcpy((void *)0xfffff000, (void *)fixup, 4096);
+               flush_cache(0xfffff000, 4096);
 
-       pq3_mp_up(bootpg);
+               disable_tlb(i);
+
+               /* setup reset page back to 1:1, we'll use HW boot translation
+                * to map this where we want
+                */
+               set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
+                       0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
+
+               pq3_mp_up(bootpg);
+       } else {
+               puts("WARNING: No reset page TLB. "
+                       "Skipping secondary core setup\n");
+       }
 }