]> git.sur5r.net Git - u-boot/blobdiff - cpu/mpc85xx/pci.c
Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdt
[u-boot] / cpu / mpc85xx / pci.c
index 84f839ae1e4fee2cf6af1212c1830899bd30abc7..d9f49c829f5dbbbd1863923625e67411134fcd68 100644 (file)
 #include <asm/cpm_85xx.h>
 #include <pci.h>
 
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
 #if defined(CONFIG_PCI)
 
 static struct pci_controller *pci_hose;
@@ -48,7 +44,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
 #ifdef CONFIG_MPC85XX_PCI2
        volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
 #endif
-       volatile ccsr_gur_t *gur = &immap->im_gur;
+       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
        struct pci_controller * hose;
 
        pci_hose = board_hose;
@@ -90,14 +86,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
        pcix->powbar1  = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
        pcix->powbear1 = 0x00000000;
        pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
-                       POWAR_MEM_WRITE | POWAR_MEM_512M);
+                       POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1));
 
        pcix->potar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
        pcix->potear2  = 0x00000000;
        pcix->powbar2  = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
        pcix->powbear2 = 0x00000000;
        pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
-                       POWAR_IO_WRITE | POWAR_IO_1M);
+                       POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1));
 
        pcix->pitar1 = 0x00000000;
        pcix->piwbar1 = 0x00000000;
@@ -142,7 +138,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
                u8 header_type;
 
                pci_hose_read_config_byte(hose,
-                                         PCI_BDF(0,17,0),
+                                         PCI_BDF(0,BRIDGE_ID,0),
                                          PCI_HEADER_TYPE,
                                          &header_type);
        }
@@ -175,14 +171,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
        pcix2->powbar1  = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
        pcix2->powbear1 = 0x00000000;
        pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
-                       POWAR_MEM_WRITE | POWAR_MEM_512M);
+                       POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1));
 
        pcix2->potar2  = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
        pcix2->potear2  = 0x00000000;
        pcix2->powbar2  = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
        pcix2->powbear2 = 0x00000000;
        pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
-                       POWAR_IO_WRITE | POWAR_IO_1M);
+                       POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1));
 
        pcix2->pitar1 = 0x00000000;
        pcix2->piwbar1 = 0x00000000;
@@ -216,27 +212,4 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
        hose->last_busno = pci_hose_scan(hose);
 #endif
 }
-
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
-       u32 *p;
-       int len;
-
-       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
-       if (p != NULL) {
-               p[0] = pci_hose[0].first_busno;
-               p[1] = pci_hose[0].last_busno;
-       }
-
-#ifdef CONFIG_MPC85XX_PCI2
-       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
-       if (p != NULL) {
-               p[0] = pci_hose[1].first_busno;
-               p[1] = pci_hose[1].last_busno;
-       }
-#endif
-}
-#endif /* CONFIG_OF_FLAT_TREE */
 #endif /* CONFIG_PCI */