li r3,0x201
mtspr SPRN_BUCSR,r3
+ /* Ensure TB is 0 */
+ li r3,0
+ mttbl r3
+ mttbu r3
+
/* Enable/invalidate the I-Cache */
mfspr r0,SPRN_L1CSR1
ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
lwz r4,ENTRY_ADDR_LOWER(r10)
andi. r11,r4,1
bne 2b
+ isync
/* get the upper bits of the addr */
lwz r11,ENTRY_ADDR_UPPER(r10)
mtspr SPRN_SRR1,r13
rfi
- .align 3
+ .align L1_CACHE_SHIFT
.globl __spin_table
__spin_table:
- .space CONFIG_NR_CPUS*ENTRY_SIZE
+ .space CONFIG_NUM_CPUS*ENTRY_SIZE
/* Fill in the empty space. The actual reset vector is
* the last word of the page */