ppc/85xx: Fix enabling of L2 cache

[u-boot] / cpu / mpc85xx / release.S

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 2d4f219a3b7e431f1f1a05f4f69154a0fd84bcdc..ecbd0d585770474704224a422a04d445caca8eff 100644 (file)
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -102,7 +102,8 @@ __secondary_start_page:
 #ifdef CONFIG_BACKSIDE_L2_CACHE
        /* Enable/invalidate the L2 cache */
        msync
-       lis     r3,L2CSR0_L2FI@h
+       lis     r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
+       ori     r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
        mtspr   SPRN_L2CSR0,r3
 1:
        mfspr   r3,SPRN_L2CSR0
@@ -168,6 +169,9 @@ __secondary_start_page:
        bne     2b
        isync
 
+       /* setup IVORs to match fixed offsets */
+#include "fixed_ivor.S"
+
        /* get the upper bits of the addr */
        lwz     r11,ENTRY_ADDR_UPPER(r10)