ppc/85xx: Fix enabling of L2 cache

[u-boot] / cpu / mpc85xx / release.S

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 75676b5b9e8bd9d88d2e3ce0b139cb070b29298e..ecbd0d585770474704224a422a04d445caca8eff 100644 (file)
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -1,3 +1,26 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Kumar Gala <kumar.gala@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
 #include <config.h>
 #include <mpc85xx.h>
 #include <version.h>
@@ -24,19 +47,28 @@
 __secondary_start_page:
 /* First do some preliminary setup */
        lis     r3, HID0_EMCP@h         /* enable machine check */
+#ifndef CONFIG_E500MC
        ori     r3,r3,HID0_TBEN@l       /* enable Timebase */
+#endif
 #ifdef CONFIG_PHYS_64BIT
        ori     r3,r3,HID0_ENMAS7@l     /* enable MAS7 updates */
 #endif
        mtspr   SPRN_HID0,r3
 
+#ifndef CONFIG_E500MC
        li      r3,(HID1_ASTME|HID1_ABE)@l      /* Addr streaming & broadcast */
        mtspr   SPRN_HID1,r3
+#endif
 
        /* Enable branch prediction */
        li      r3,0x201
        mtspr   SPRN_BUCSR,r3
 
+       /* Ensure TB is 0 */
+       li      r3,0
+       mttbl   r3
+       mttbu   r3
+
        /* Enable/invalidate the I-Cache */
        mfspr   r0,SPRN_L1CSR1
        ori     r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
@@ -59,10 +91,31 @@ __secondary_start_page:
 
        /* r10 has the base address for the entry */
        mfspr   r0,SPRN_PIR
+#ifdef CONFIG_E500MC
+       rlwinm  r4,r0,27,27,31
+#else
        mr      r4,r0
+#endif
        slwi    r8,r4,5
        add     r10,r3,r8
 
+#ifdef CONFIG_BACKSIDE_L2_CACHE
+       /* Enable/invalidate the L2 cache */
+       msync
+       lis     r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
+       ori     r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
+       mtspr   SPRN_L2CSR0,r3
+1:
+       mfspr   r3,SPRN_L2CSR0
+       andis.  r1,r3,L2CSR0_L2FI@h
+       bne     1b
+
+       lis     r3,CONFIG_SYS_INIT_L2CSR0@h
+       ori     r3,r3,CONFIG_SYS_INIT_L2CSR0@l
+       mtspr   SPRN_L2CSR0,r3
+       isync
+#endif
+
 #define EPAPR_MAGIC            (0x45504150)
 #define ENTRY_ADDR_UPPER       0
 #define ENTRY_ADDR_LOWER       4
@@ -116,6 +169,9 @@ __secondary_start_page:
        bne     2b
        isync
 
+       /* setup IVORs to match fixed offsets */
+#include "fixed_ivor.S"
+
        /* get the upper bits of the addr */
        lwz     r11,ENTRY_ADDR_UPPER(r10)
 
@@ -144,6 +200,7 @@ __secondary_start_page:
        mfspr   r0,SPRN_PIR
        stw     r0,ENTRY_PIR(r10)
 
+       mtspr   IVPR,r12
 /*
  * Coming here, we know the cpu has one TLB mapping in TLB1[0]
  * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
@@ -173,7 +230,7 @@ __secondary_start_page:
        .align L1_CACHE_SHIFT
        .globl __spin_table
 __spin_table:
-       .space CONFIG_NUM_CPUS*ENTRY_SIZE
+       .space CONFIG_MAX_CPUS*ENTRY_SIZE
 
        /* Fill in the empty space.  The actual reset vector is
         * the last word of the page */