Reworked FSL Book-E TLB macros to be more readable

[u-boot] / cpu / mpc85xx / spd_sdram.c

diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 553f736a56a07d2d64bf21166a96eef900ce522d..adc9c4dd40ec356d241569a2e4ca00aebabb1690 100644 (file)
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -1071,22 +1071,19 @@ setup_laws_and_tlbs(unsigned int memsize)
        ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
        while (ram_tlb_address < (memsize * 1024 * 1024)
              && ram_tlb_index < 16) {
-               mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
-               mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
-               mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
-                                     0, 0, 0, 0, 0, 0, 0, 0));
-               mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
-                                     0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+               mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
+               mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
+               mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0));
+               mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0,
+                       (MAS3_SX|MAS3_SW|MAS3_SR)));
                asm volatile("isync;msync;tlbwe;isync");
 
-               debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
-               debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
-               debug("DDR: MAS2=0x%08x\n",
-                     TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
-                               0, 0, 0, 0, 0, 0, 0, 0));
+               debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
+               debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
+               debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0));
                debug("DDR: MAS3=0x%08x\n",
-                     TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
-                               0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+                       FSL_BOOKE_MAS3(ram_tlb_address, 0,
+                                     (MAS3_SX|MAS3_SW|MAS3_SR)));
 
                ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
                ram_tlb_index++;