Merge branch 'fixes'

[u-boot] / cpu / mpc85xx / speed.c

diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 699441b46a48c97b87247b5d28201d1ff6b5e9e8..0d55228b641f7ba9cc8b298cc6f8fcd3cac1ec15 100644 (file)
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <ppc_asm.tmpl>
 #include <asm/processor.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -35,8 +36,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info (sys_info_t * sysInfo)
 {
-       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        uint plat_ratio,e500_ratio,half_freqSystemBus;
+       uint lcrr_div;
 
        plat_ratio = (gur->porpllsr) & 0x0000003e;
        plat_ratio >>= 1;
@@ -54,11 +56,36 @@ void get_sys_info (sys_info_t * sysInfo)
 
 #ifdef CONFIG_DDR_CLK_FREQ
        {
-               u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+               u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+                       >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
                if (ddr_ratio != 0x7)
                        sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
        }
 #endif
+
+#if defined(CONFIG_SYS_LBC_LCRR)
+       /* We will program LCRR to this value later */
+       lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
+#else
+       {
+           volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+           lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
+       }
+#endif
+       if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
+#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
+    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
+               /*
+                * Yes, the entire PQ38 family use the same
+                * bit-representation for twice the clock divider values.
+                */
+               lcrr_div *= 2;
+#endif
+               sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
+       } else {
+               /* In case anyone cares what the unknown value is */
+               sysInfo->freqLocalBus = lcrr_div;
+       }
 }
 
 
@@ -66,10 +93,10 @@ int get_clocks (void)
 {
        sys_info_t sys_info;
 #ifdef CONFIG_MPC8544
-       volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR;
+       volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
 #endif
 #if defined(CONFIG_CPM2)
-       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
        uint sccr, dfbrg;
 
        /* set VCO = 4 * BRG */
@@ -81,6 +108,7 @@ int get_clocks (void)
        gd->cpu_clk = sys_info.freqProcessor;
        gd->bus_clk = sys_info.freqSystemBus;
        gd->mem_clk = sys_info.freqDDRBus;
+       gd->lbc_clk = sys_info.freqLocalBus;
 
        /*
         * The base clock for I2C depends on the actual SOC.  Unfortunately,
@@ -110,6 +138,10 @@ int get_clocks (void)
 #endif
        gd->i2c2_clk = gd->i2c1_clk;
 
+#if defined(CONFIG_MPC8536)
+       gd->sdhc_clk = gd->bus_clk / 2;
+#endif
+
 #if defined(CONFIG_CPM2)
        gd->vco_out = 2*sys_info.freqSystemBus;
        gd->cpm_clk = gd->vco_out / 2;