Coding stylke cleanup; update CHANGELOG.

[u-boot] / cpu / mpc85xx / start.S

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 5f75bc1aff9e69175671616261acb0489bc87fb9..20c7ebc7238bee98e06fed91cd3ea60b1df3da03 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -251,13 +251,10 @@ _start_e500:
         */
        bl      tlb1_entry
        mr      r5,r0
-       li      r1,0x0020       /* max 16 TLB1 plus some TLB0 entries */
-       mtctr   r1
        lwzu    r4,0(r5)        /* how many TLB1 entries we actually use */
+       mtctr   r4
 
-0:     cmpwi   r4,0
-       beq     1f
-       lwzu    r0,4(r5)
+0:     lwzu    r0,4(r5)
        lwzu    r1,4(r5)
        lwzu    r2,4(r5)
        lwzu    r3,4(r5)
@@ -269,7 +266,6 @@ _start_e500:
        msync
        tlbwe
        isync
-       addi    r4,r4,-1
        bdnz    0b
 
 1:
@@ -301,20 +297,16 @@ _start_e500:
 
        bl      law_entry
        mr      r6,r0
-       li      r1,0x0007       /* 8 LAWs, but reserve one for boot-over-rio-or-pci */
-       mtctr   r1
        lwzu    r5,0(r6)        /* how many windows we actually use */
+       mtctr   r5
 
        li      r2,0x0c28       /* the first pair is reserved for boot-over-rio-or-pci */
        li      r1,0x0c30
 
-0:     cmpwi   r5,0
-       beq     1f
-       lwzu    r4,4(r6)
+0:     lwzu    r4,4(r6)
        lwzu    r3,4(r6)
        stwx    r4,r7,r2
        stwx    r3,r7,r1
-       addi    r5,r5,-1
        addi    r2,r2,0x0020
        addi    r1,r1,0x0020
        bdnz    0b
@@ -715,7 +707,7 @@ icache_disable:
        .globl  icache_status
 icache_status:
        mfspr   r3,L1CSR1
-       srwi    r3, r3, 31      /* >>31 => select bit 0 */
+       andi.   r3,r3,1
        blr
 
        .globl  dcache_enable
@@ -748,7 +740,7 @@ dcache_disable:
        .globl  dcache_status
 dcache_status:
        mfspr   r3,L1CSR0
-       srwi    r3, r3, 31      /* >>31 => select bit 0 */
+       andi.   r3,r3,1
        blr
 
        .globl get_pir
@@ -995,6 +987,11 @@ relocate_code:
 7:     sync                    /* Wait for all icbi to complete on bus */
        isync
 
+       /*
+        * Re-point the IVPR at RAM
+        */
+       mtspr   IVPR,r10
+
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.