sbc8548: remove eTSEC3/4 voltage hack

[u-boot] / cpu / mpc85xx / start.S

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 80f96773e90e7426476cc879af433518e42aaf40..c9e91a90da696cfa4b22b11ce12b94106bfdd76f 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright 2004, 2007-2009 Freescale Semiconductor.
  * Copyright (C) 2003  Motorola,Inc.
  *
  * See file CREDITS for list of people who contributed to this
@@ -57,10 +57,12 @@
        GOT_ENTRY(_GOT2_TABLE_)
        GOT_ENTRY(_FIXUP_TABLE_)
 
+#ifndef CONFIG_NAND_SPL
        GOT_ENTRY(_start)
        GOT_ENTRY(_start_of_vectors)
        GOT_ENTRY(_end_of_vectors)
        GOT_ENTRY(transfer_to_handler)
+#endif
 
        GOT_ENTRY(__init_end)
        GOT_ENTRY(_end)
@@ -156,12 +158,18 @@ _start_e500:
        mtspr   MCSR,r0                 /* machine check syndrome register */
        mtxer   r0                      /* clear integer exception register */
 
+#ifdef CONFIG_SYS_BOOK3E_HV
+       mtspr   MAS8,r0                 /* make sure MAS8 is clear */
+#endif
+
        /* Enable Time Base and Select Time Base Clock */
        lis     r0,HID0_EMCP@h          /* Enable machine check */
 #if defined(CONFIG_ENABLE_36BIT_PHYS)
        ori     r0,r0,HID0_ENMAS7@l     /* Enable MAS7 */
 #endif
+#ifndef CONFIG_E500MC
        ori     r0,r0,HID0_TBEN@l       /* Enable Timebase */
+#endif
        mtspr   HID0,r0
 
 #ifndef CONFIG_E500MC
@@ -184,10 +192,60 @@ _start_e500:
        mtspr   DBCR0,r0
 #endif
 
-       /* create a temp mapping in AS=1 to the 4M boot window */
+#ifdef CONFIG_MPC8569
+#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
+#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
+
+       /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
+        * use address space which is more than 12bits, and it must be done in
+        * the 4K boot page. So we set this bit here.
+        */
+
+       /* create a temp mapping TLB0[0] for LBCR  */
+       lis     r6,FSL_BOOKE_MAS0(0, 0, 0)@h
+       ori     r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
+
+       lis     r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
+       ori     r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
+
+       lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
+       ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
+
+       lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
+                                               (MAS3_SX|MAS3_SW|MAS3_SR))@h
+       ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
+                                               (MAS3_SX|MAS3_SW|MAS3_SR))@l
+
+       mtspr   MAS0,r6
+       mtspr   MAS1,r7
+       mtspr   MAS2,r8
+       mtspr   MAS3,r9
+       isync
+       msync
+       tlbwe
+
+       /* Set LBCR register */
+       lis     r4,CONFIG_SYS_LBCR_ADDR@h
+       ori     r4,r4,CONFIG_SYS_LBCR_ADDR@l
+
+       lis     r5,CONFIG_SYS_LBC_LBCR@h
+       ori     r5,r5,CONFIG_SYS_LBC_LBCR@l
+       stw     r5,0(r4)
+       isync
+
+       /* invalidate this temp TLB */
+       lis     r4,CONFIG_SYS_LBC_ADDR@h
+       ori     r4,r4,CONFIG_SYS_LBC_ADDR@l
+       tlbivax 0,r4
+       isync
+
+#endif /* CONFIG_MPC8569 */
+
        lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
        ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
 
+#ifndef CONFIG_SYS_RAMBOOT
+       /* create a temp mapping in AS=1 to the 4M boot window */
        lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
        ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
 
@@ -197,6 +255,20 @@ _start_e500:
        /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
        lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
        ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#else
+       /*
+        * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
+        * image has been relocated to TEXT_BASE on the second stage.
+        */
+       lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
+       ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
+
+       lis     r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
+       ori     r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+
+       lis     r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+       ori     r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#endif
 
        mtspr   MAS0,r6
        mtspr   MAS1,r7
@@ -227,8 +299,8 @@ _start_e500:
        msync
        tlbwe
 
-       lis     r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h
-       ori     r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l
+       lis     r6,MSR_IS|MSR_DS@h
+       ori     r6,r6,MSR_IS|MSR_DS@l
        lis     r7,switch_as@h
        ori     r7,r7,switch_as@l
 
@@ -308,6 +380,7 @@ _start_cont:
        bl      board_init_f
        isync
 
+#ifndef CONFIG_NAND_SPL
        . = EXC_OFF_SYS_RESET
        .globl  _start_of_vectors
 _start_of_vectors:
@@ -762,9 +835,32 @@ in32:
 in32r:
        lwbrx   r3,r0,r3
        blr
+#endif  /* !CONFIG_NAND_SPL */
 
 /*------------------------------------------------------------------------------*/
 
+/*
+ * void write_tlb(mas0, mas1, mas2, mas3, mas7)
+ */
+       .globl  write_tlb
+write_tlb:
+       mtspr   MAS0,r3
+       mtspr   MAS1,r4
+       mtspr   MAS2,r5
+       mtspr   MAS3,r6
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+       mtspr   MAS7,r7
+#endif
+       li      r3,0
+#ifdef CONFIG_SYS_BOOK3E_HV
+       mtspr   MAS8,r3
+#endif
+       isync
+       tlbwe
+       msync
+       isync
+       blr
+
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -924,6 +1020,7 @@ clear_bss:
        mr      r4,r10          /* Destination Address          */
        bl      board_init_r
 
+#ifndef CONFIG_NAND_SPL
        /*
         * Copy exception vector code to low memory
         *
@@ -1071,3 +1168,10 @@ flush_dcache:
        isync
 
        blr
+
+.globl setup_ivors
+setup_ivors:
+
+#include "fixed_ivor.S"
+       blr
+#endif /* !CONFIG_NAND_SPL */