.globl icache_status
icache_status:
mfspr r3,L1CSR1
- srwi r3, r3, 31 /* >>31 => select bit 0 */
+ andi. r3,r3,1
blr
.globl dcache_enable
.globl dcache_status
dcache_status:
mfspr r3,L1CSR0
- srwi r3, r3, 31 /* >>31 => select bit 0 */
+ andi. r3,r3,1
blr
.globl get_pir
7: sync /* Wait for all icbi to complete on bus */
isync
+ /*
+ * Re-point the IVPR at RAM
+ */
+ mtspr IVPR,r10
+
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.