Merge branch 'master' of rsync://rsync.denx.de/git/u-boot

[u-boot] / cpu / mpc85xx / start.S

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index af28ebe33fcb52b7c87f5871d2a3a8fd68cc72d4..f96a4c3f8b0dcd2d0cf9ef2ebb719b50fbbadb98 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -155,11 +155,13 @@ _start_e500:
        mtspr   MCSR,r0
        mtspr   DEAR,r0
 
-       mtspr   DBCR0,r0
+       /* not needed and conflicts with some debuggers */
+       /* mtspr        DBCR0,r0 */
        mtspr   DBCR1,r0
        mtspr   DBCR2,r0
-       mtspr   IAC1,r0
-       mtspr   IAC2,r0
+       /* not needed and conflicts with some debuggers */
+       /* mtspr        IAC1,r0 */
+       /* mtspr        IAC2,r0 */
        mtspr   DAC1,r0
        mtspr   DAC2,r0
 
@@ -174,6 +176,9 @@ _start_e500:
        mtspr   BUCSR,r0        /* disable branch prediction */
        mtspr   MAS4,r0
        mtspr   MAS6,r0
+#if defined(CONFIG_ENABLE_36BIT_PHYS)
+       mtspr   MAS7,r0
+#endif
        isync
 
        /* Setup interrupt vectors */
@@ -358,6 +363,9 @@ _start:
        /* Enable Time Base and Select Time Base Clock */
        lis     r0,HID0_EMCP@h          /* Enable machine check */
        ori     r0,r0,0x4000            /* time base is processor clock */
+#if defined(CONFIG_ENABLE_36BIT_PHYS)
+       ori     r0,r0,0x0080            /* enable MAS7 updates */
+#endif
        mtspr   HID0,r0
 
 #if defined(CONFIG_ADDR_STREAMING)
@@ -707,7 +715,7 @@ icache_disable:
        .globl  icache_status
 icache_status:
        mfspr   r3,L1CSR1
-       srwi    r3, r3, 31      /* >>31 => select bit 0 */
+       andi.   r3,r3,1
        blr
 
        .globl  dcache_enable
@@ -740,7 +748,7 @@ dcache_disable:
        .globl  dcache_status
 dcache_status:
        mfspr   r3,L1CSR0
-       srwi    r3, r3, 31      /* >>31 => select bit 0 */
+       andi.   r3,r3,1
        blr
 
        .globl get_pir
@@ -987,6 +995,11 @@ relocate_code:
 7:     sync                    /* Wait for all icbi to complete on bus */
        isync
 
+       /*
+        * Re-point the IVPR at RAM
+        */
+       mtspr   IVPR,r10
+
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.