Blackfin: update on-chip ROM API

[u-boot] / cpu / mpc85xx / tlb.c

diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 7ce7a14b849eb02495632661124e2010186d6da0..25fa9ee8f8e65cc93e8f0ad0e87a1c69aac3af49 100644 (file)
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -26,6 +26,11 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#ifdef CONFIG_ADDR_MAP
+#include <addr_map.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
 
 void set_tlb(u8 tlb, u32 epn, u64 rpn,
             u8 perms, u8 wimge,
@@ -47,6 +52,11 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
        mtspr(MAS7, _mas7);
 #endif
        asm volatile("isync;msync;tlbwe;isync");
+
+#ifdef CONFIG_ADDR_MAP
+       if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
+               addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
+#endif
 }
 
 void disable_tlb(u8 esel)
@@ -67,6 +77,11 @@ void disable_tlb(u8 esel)
        mtspr(MAS7, _mas7);
 #endif
        asm volatile("isync;msync;tlbwe;isync");
+
+#ifdef CONFIG_ADDR_MAP
+       if (gd->flags & GD_FLG_RELOC)
+               addrmap_set_entry(0, 0, 0, esel);
+#endif
 }
 
 void invalidate_tlb(u8 tlb)
@@ -91,6 +106,29 @@ void init_tlbs(void)
        return ;
 }
 
+#ifdef CONFIG_ADDR_MAP
+void init_addr_map(void)
+{
+       int i;
+
+       for (i = 0; i < num_tlb_entries; i++) {
+               if (tlb_table[i].tlb == 0)
+                       continue;
+
+               addrmap_set_entry(tlb_table[i].epn,
+                       tlb_table[i].rpn,
+                       (1UL << ((tlb_table[i].tsize * 2) + 10)),
+                       tlb_table[i].esel);
+       }
+
+       return ;
+}
+#endif
+
+#ifndef CONFIG_SYS_DDR_TLB_START
+#define CONFIG_SYS_DDR_TLB_START 8
+#endif
+
 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 {
        unsigned int tlb_size;
@@ -137,8 +175,8 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
         * Configure DDR TLB1 entries.
         * Starting at TLB1 8, use no more than 8 TLB1 entries.
         */
-       ram_tlb_index = 8;
-       ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
+       ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
+       ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
        while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
              && ram_tlb_index < 16) {
                set_tlb(1, ram_tlb_address, ram_tlb_address,