Change DDR tlb start entry to CONFIG param for 85xx

[u-boot] / cpu / mpc85xx / tlb.c

diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 5b5f7914f2ce0d4f788e5b4329717f443a7a765a..25fa9ee8f8e65cc93e8f0ad0e87a1c69aac3af49 100644 (file)
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -125,6 +125,10 @@ void init_addr_map(void)
 }
 #endif
 
+#ifndef CONFIG_SYS_DDR_TLB_START
+#define CONFIG_SYS_DDR_TLB_START 8
+#endif
+
 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 {
        unsigned int tlb_size;
@@ -171,7 +175,7 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
         * Configure DDR TLB1 entries.
         * Starting at TLB1 8, use no more than 8 TLB1 entries.
         */
-       ram_tlb_index = 8;
+       ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
        ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
        while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
              && ram_tlb_index < 16) {