#include <ft_build.h>
#endif
+extern unsigned long get_board_sys_clk(ulong dummy);
-// SS: For debug only, remove after use
static __inline__ unsigned long get_dbat3u (void)
{
- unsigned long dbat3u;
- asm volatile("mfspr %0, 542" : "=r" (dbat3u) :);
- return dbat3u;
+ unsigned long dbat3u;
+ asm volatile("mfspr %0, 542" : "=r" (dbat3u) :);
+ return dbat3u;
}
static __inline__ unsigned long get_dbat3l (void)
{
- unsigned long dbat3l;
- asm volatile("mfspr %0, 543" : "=r" (dbat3l) :);
- return dbat3l;
+ unsigned long dbat3l;
+ asm volatile("mfspr %0, 543" : "=r" (dbat3l) :);
+ return dbat3l;
}
static __inline__ unsigned long get_msr (void)
{
- unsigned long msr;
- asm volatile("mfmsr %0" : "=r" (msr) :);
- return msr;
+ unsigned long msr;
+ asm volatile("mfmsr %0" : "=r" (msr) :);
+ return msr;
}
-extern unsigned long get_board_sys_clk(ulong dummy);
int checkcpu (void)
{
uint major, minor;
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
-
+
puts("Freescale PowerPC\n");
pvr = get_pvr();
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
- puts ("CPU:\n");
+ puts("CPU:\n");
printf(" Core: ");
-
+
switch (ver) {
case PVR_VER(PVR_86xx):
puts("E600");
minor = SVR_MIN(svr);
puts(" System: ");
- switch (ver) {
+ switch (ver) {
case SVR_8641:
puts("8641");
break;
printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
-
+
#if defined(CFG_LBC_LCRR)
lcrr = CFG_LBC_LCRR;
#else
printf(" L2: ");
if (get_l2cr() & 0x80000000)
- printf("Enabled\n");
+ printf("Enabled\n");
else
- printf("Disabled\n");
-
- return (0);
+ printf("Disabled\n");
+
+ return 0;
}
{
#ifndef CONFIG_MPC8641HPCN
-
+
/* SRR0 has system reset vector, SRR1 has default MSR value */
/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
sysclk_s = 0x06;
sysclk_r = 0x1F;
sysclk_v = 0x3B;
- sysclk_aux = 0x06;
+ sysclk_aux = 0x06;
break;
case 166:
sysclk_s = 0x06;
printf("Unsupported SYSCLK frequency.\n");
return 0;
}
-
+
vclkh = (sysclk_s << 5) | sysclk_r ;
vclkl = sysclk_v;
out8(PIXIS_BASE+PIXIS_VCLKH,vclkh);
out8(PIXIS_BASE+PIXIS_VCLKL,vclkl);
out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux);
-
+
return 1;
}
tmp = in8(PIXIS_BASE+PIXIS_VSPEED1);
tmp = (tmp & 0xF0) | (val & 0x0F);
out8(PIXIS_BASE+PIXIS_VSPEED1,tmp);
-
+
return 1;
}
{
u8 tmp;
u8 val;
-
- switch((int)corepll)
- {
+
+ switch ((int)corepll) {
case 20:
val = 0x08;
break;
printf("Unsupported COREPLL ratio.\n");
return 0;
}
-
+
tmp = in8(PIXIS_BASE+PIXIS_VSPEED0);
tmp = (tmp & 0xE0) | (val & 0x1F);
out8(PIXIS_BASE+PIXIS_VSPEED0,tmp);
-
+
return 1;
}
tmp = tmp | mask;
else
tmp = tmp & ~mask;
- out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp);
+ out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp);
}
void read_from_px_regs_altbank(int set)
tmp = tmp | mask;
else
tmp = tmp & ~mask;
- out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp);
+ out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp);
}
void set_altbank(void)
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
tmp = tmp | 0x01;
- out8(PIXIS_BASE+PIXIS_VCTL,tmp);
+ out8(PIXIS_BASE+PIXIS_VCTL,tmp);
}
void set_px_go_with_watchdog(void)
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
tmp = tmp | 0x09;
- out8(PIXIS_BASE+PIXIS_VCTL,tmp);
+ out8(PIXIS_BASE+PIXIS_VCTL,tmp);
}
/* This function takes the non-integral cpu:mpx pll ratio
no_dec = 1;
break; /* Break from loop once the end of string is reached */
}
-
+
intarr[i] = strptr[i];
i++;
}
-
+
intarr_len = i; /* Assign length of integer part to intarr_len*/
intarr[i] = '\0'; /* */
i++;
j++;
}
-
+
decarr_len = j;
decarr[j] = '\0';
-
+
mulconst=1;
for(i=0; i<decarr_len;i++)
mulconst = mulconst*10;
- decval = simple_strtoul(decarr,NULL,10);
+ decval = simple_strtoul(decarr,NULL,10);
}
intval = simple_strtoul(intarr,NULL,10);
return retval;
}
-
-#endif //CONFIG_MPC8641HPCN
+
+#endif /* CONFIG_MPC8641HPCN */
/* no generic way to do board reset. simply call soft_reset. */
char cmd;
ulong addr, val;
ulong corepll;
-
-
#ifdef CFG_RESET_ADDRESS
addr = CFG_RESET_ADDRESS;
#ifndef CONFIG_MPC8641HPCN
- /* flush and disable I/D cache */
+ /* flush and disable I/D cache */
__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
__asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
soft_restart(addr);
#else /* CONFIG_MPC8641HPCN */
-
- if(argc > 1)
- {
- cmd = argv[1][1];
- switch(cmd)
- {
- case 'f': /* reset with frequency changed */
-
- if (argc < 5)
- goto my_usage;
-
- read_from_px_regs(0);
-
- val = set_px_sysclk(simple_strtoul(argv[2],NULL,10));
-
- corepll = strfractoint(argv[3]);
- val = val + set_px_corepll(corepll);
- val = val + set_px_mpxpll(simple_strtoul(argv[4],NULL,10));
- if(val == 3)
- {
- printf("Setting registers VCFGEN0 and VCTL\n");
- read_from_px_regs(1);
- printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
- set_px_go();
- }
- else
- goto my_usage;
-
- while(1); /* Not reached */
-
- case 'l':
- if(argv[2][1] == 'f')
- {
- read_from_px_regs(0);
- read_from_px_regs_altbank(0);
- /* reset with frequency changed */
- val = set_px_sysclk(simple_strtoul(argv[3],NULL,10));
-
- corepll = strfractoint(argv[4]);
- val = val + set_px_corepll(corepll);
- val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10));
- if(val == 3)
- {
- printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
- set_altbank();
- read_from_px_regs(1);
- read_from_px_regs_altbank(1);
- printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
- set_px_go_with_watchdog();
-
- }
- else
- goto my_usage;
-
- while(1); /* Not reached */
- }
- else /* Reset from next bank without changing frequencies */
- {
- read_from_px_regs(0);
- read_from_px_regs_altbank(0);
- if(argc > 2)
- goto my_usage;
- printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
- set_altbank();
- read_from_px_regs_altbank(1);
- printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
- set_px_go_with_watchdog();
- while(1); /* Not reached */
- }
-
- default:
- goto my_usage;
- }
+
+ if (argc > 1) {
+ cmd = argv[1][1];
+ switch(cmd) {
+ case 'f': /* reset with frequency changed */
+ if (argc < 5)
+ goto my_usage;
+ read_from_px_regs(0);
+
+ val = set_px_sysclk(simple_strtoul(argv[2],NULL,10));
+
+ corepll = strfractoint(argv[3]);
+ val = val + set_px_corepll(corepll);
+ val = val + set_px_mpxpll(simple_strtoul(argv[4],
+ NULL, 10));
+ if (val == 3) {
+ printf("Setting registers VCFGEN0 and VCTL\n");
+ read_from_px_regs(1);
+ printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
+ set_px_go();
+ } else
+ goto my_usage;
+
+ while (1); /* Not reached */
+
+ case 'l':
+ if (argv[2][1] == 'f') {
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ /* reset with frequency changed */
+ val = set_px_sysclk(simple_strtoul(argv[3],NULL,10));
+
+ corepll = strfractoint(argv[4]);
+ val = val + set_px_corepll(corepll);
+ val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10));
+ if (val == 3) {
+ printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs(1);
+ read_from_px_regs_altbank(1);
+ printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
+ set_px_go_with_watchdog();
+ } else
+ goto my_usage;
+
+ while(1); /* Not reached */
+ } else {
+ /* Reset from next bank without changing frequencies */
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ if(argc > 2)
+ goto my_usage;
+ printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs_altbank(1);
+ printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
+ set_px_go_with_watchdog();
+ while(1); /* Not reached */
+ }
+
+ default:
+ goto my_usage;
+ }
+
my_usage:
- printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
- printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
- printf("For example: reset cf 40 2.5 10\n");
- printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
- return;
- }
- else
- out8(PIXIS_BASE+PIXIS_RST,0);
-
+ printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
+ printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
+ printf("For example: reset cf 40 2.5 10\n");
+ printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
+ return;
+ } else
+ out8(PIXIS_BASE+PIXIS_RST,0);
+
#endif /* !CONFIG_MPC8641HPCN */
-
+
while(1); /* not reached */
}
-/* ------------------------------------------------------------------------- */
-
/*
* Get timebase clock frequency
*/
sys_info_t sys_info;
get_sys_info(&sys_info);
- return ((sys_info.freqSystemBus + 3L) / 4L);
-
+ return (sys_info.freqSystemBus + 3L) / 4L;
}
-/* ------------------------------------------------------------------------- */
#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
-
}
#endif /* CONFIG_WATCHDOG */
-/* ------------------------------------------------------------------------- */
#if defined(CONFIG_DDR_ECC)
-void dma_init(void) {
+void dma_init(void)
+{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
return;
}
-uint dma_check(void) {
+uint dma_check(void)
+{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
volatile uint status = dma->sr0;
return status;
}
-int dma_xfer(void *dest, uint count, void *src) {
+int dma_xfer(void *dest, uint count, void *src)
+{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
asm("sync;isync");
return dma_check();
}
+
#endif /* CONFIG_DDR_ECC */
u32 *p;
ulong clock;
int len;
-
+
clock = bd->bi_busfreq;
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
if (p != NULL)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
memcpy(p, bd->bi_enetaddr, 6);
#endif
-
+
#if defined(CONFIG_MPC86XX_TSEC2)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
memcpy(p, bd->bi_enet1addr, 6);
projects / u-boot / blobdiff