/*
* Copyright 2004 Freescale Semiconductor.
- * Jeff Brown (jeffrey@freescale.com)
+ * Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <mpc86xx.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Breathe some life into the CPU...
*
void cpu_init_f(void)
{
- DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
- /* Pointer is writable since we allocated a register for it */
+ /* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
+#ifdef CONFIG_FSL_LAW
+ init_laws();
+#endif
+
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x4000000);
- /* enable SYNCBE | ABE bits in HID1 */
- set_hid1(get_hid1() | 0x00000C00);
-
- /* Since the bats have been set up at this point and
- * the local bus registers have been initialized, we
- * turn on the WDEN bit in PIXIS_VCTL
- */
-/* val = in8(PIXIS_BASE+PIXIS_VCTL); */
- /* Set the WDEN */
-/* val |= 0x08; */
-/* out8(PIXIS_BASE+PIXIS_VCTL,val); */
+ /* enable EMCP, SYNCBE | ABE bits in HID1 */
+ set_hid1(get_hid1() | 0x80000C00);
}
/*
*/
int cpu_init_r(void)
{
+#ifdef CONFIG_FSL_LAW
+ disable_law(0);
+#endif
return 0;
}
-
-
-
-
-