8xx: Update OF support on 8xx

[u-boot] / cpu / mpc8xx / cpu.c

diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c
index 3fb97b07ca7df092e61a584f891e09200a5388e4..a86598e32e7aef70c810d6cae2b9d95eff791a57 100644 (file)
--- a/cpu/mpc8xx/cpu.c
+++ b/cpu/mpc8xx/cpu.c
@@ -39,6 +39,14 @@
 #include <mpc8xx.h>
 #include <asm/cache.h>
 
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
 static char *cpu_warning = "\n         " \
        "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
 
@@ -69,14 +77,15 @@ static int check_CPU (long clock, uint pvr, uint immr)
 
        k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
        m = 0;
+       suf = "";
 
        /*
         * Some boards use sockets so different CPUs can be used.
         * We have to check chip version in run time.
         */
        switch (k) {
-       case 0x00020001: pre = 'P'; suf = ""; break;
-       case 0x00030001: suf = ""; break;
+       case 0x00020001: pre = 'P'; break;
+       case 0x00030001: break;
        case 0x00120003: suf = "A"; break;
        case 0x00130003: suf = "A3"; break;
 
@@ -93,7 +102,11 @@ static int check_CPU (long clock, uint pvr, uint immr)
                /* this value is not documented anywhere */
        case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
                /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
-       case 0x08000003: pre = 'M'; suf = ""; m = 1;
+       case 0x08010004:                /* Rev. A.0 */
+               suf = "A";
+               /* fall through */
+       case 0x08000003:                /* Rev. 0.3 */
+               pre = 'M'; m = 1;
                if (id_str == NULL)
                        id_str =
 # if defined(CONFIG_MPC852T)
@@ -123,12 +136,24 @@ static int check_CPU (long clock, uint pvr, uint immr)
        else
                printf ("unknown M%s (0x%08x)", id_str, k);
 
-       printf (" at %s MHz:", strmhz (buf, clock));
 
-       printf (" %u kB I-Cache", checkicache () >> 10);
-       printf (" %u kB D-Cache", checkdcache () >> 10);
+#if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX)
+       printf (" at %s MHz [%d.%d...%d.%d MHz]\n       ",
+               strmhz (buf, clock),
+               CFG_8xx_CPUCLK_MIN / 1000000,
+               ((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
+               CFG_8xx_CPUCLK_MAX / 1000000,
+               ((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
+       );
+#else
+       printf (" at %s MHz: ", strmhz (buf, clock));
+#endif
+       printf ("%u kB I-Cache %u kB D-Cache",
+               checkicache () >> 10,
+               checkdcache () >> 10
+       );
 
-       /* do we have a FEC (860T/P or 852/859/866)? */
+       /* do we have a FEC (860T/P or 852/859/866/885)? */
 
        immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
        if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
@@ -178,10 +203,17 @@ static int check_CPU (long clock, uint pvr, uint immr)
        default: suf = NULL; break;
        }
 
+#ifndef CONFIG_MPC857
        if (suf)
                printf ("%cPC862%sZPnn%s", pre, mid, suf);
        else
                printf ("unknown MPC862 (0x%08x)", k);
+#else
+       if (suf)
+               printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
+       else
+               printf ("unknown MPC857 (0x%08x)", k);
+#endif
 
        printf (" at %s MHz:", strmhz (buf, clock));
 
@@ -325,8 +357,6 @@ static int check_CPU (long clock, uint pvr, uint immr)
 
 int checkcpu (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong clock = gd->cpu_clk;
        uint immr = get_immr (0);       /* Return full IMMR contents */
        uint pvr = get_pvr ();
@@ -444,6 +474,8 @@ void upmconfig (uint upm, uint * table, uint size)
 
 /* ------------------------------------------------------------------------- */
 
+#ifndef CONFIG_LWMON
+
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
        ulong msr, addr;
@@ -478,6 +510,32 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        return 1;
 }
 
+#else  /* CONFIG_LWMON */
+
+/*
+ * On the LWMON board, the MCLR reset input of the PIC's on the board
+ * uses a 47K/1n RC combination which has a 47us time  constant.  The
+ * low  signal on the HRESET pin of the CPU is only 512 clocks = 8 us
+ * and thus too short to reset the external hardware. So we  use  the
+ * watchdog to reset the board.
+ */
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+       /* prevent triggering the watchdog */
+       disable_interrupts ();
+
+       /* make sure the watchdog is running */
+       reset_8xx_watchdog ((immap_t *) CFG_IMMR);
+
+       /* wait for watchdog reset */
+       while (1) {};
+
+       /* NOTREACHED */
+       return 1;
+}
+
+#endif /* CONFIG_LWMON */
+
 /* ------------------------------------------------------------------------- */
 
 /*
@@ -487,8 +545,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uint immr = get_immr (0);       /* Return full IMMR contents */
        volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
        ulong oscclk, factor, pll;
@@ -539,6 +595,9 @@ void watchdog_reset (void)
        if (re_enable)
                enable_interrupts ();
 }
+#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
 
 void reset_8xx_watchdog (volatile immap_t * immr)
 {
@@ -555,6 +614,17 @@ void reset_8xx_watchdog (volatile immap_t * immr)
        immr->im_ioport.iop_padir |= WATCHDOG_BIT;      /* Output   */
        immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT);   /* active output */
 
+       immr->im_ioport.iop_padat ^= WATCHDOG_BIT;      /* Toggle WDI   */
+# elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
+       /*
+        * The KUP4 boards uses a TPS3705 Watchdog
+        * with the trigger pin connected to port PA.5
+        */
+# define WATCHDOG_BIT  0x0400
+       immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT);   /* GPIO     */
+       immr->im_ioport.iop_padir |= WATCHDOG_BIT;      /* Output   */
+       immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT);   /* active output */
+
        immr->im_ioport.iop_padat ^= WATCHDOG_BIT;      /* Toggle WDI   */
 # else
        /*
@@ -567,4 +637,3 @@ void reset_8xx_watchdog (volatile immap_t * immr)
 
 #endif /* CONFIG_WATCHDOG */
 
-/* ------------------------------------------------------------------------- */