Merge branch 'master' of /home/wd/git/u-boot/lwmon5

[u-boot] / cpu / mpc8xx / speed.c

diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index 95003ed9c114e0c39045f83220554c3b0718ea7c..070babcc9a3b4f88b0c30d22f82e3b4aa620da54 100644 (file)
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -25,7 +25,9 @@
 #include <mpc8xx.h>
 #include <asm/processor.h>
 
-#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK)
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG)
 
 #define PITC_SHIFT 16
 #define PITR_SHIFT 16
@@ -172,6 +174,27 @@ unsigned long measure_gclk(void)
 
 #endif
 
+void get_brgclk(uint sccr)
+{
+       uint divider = 0;
+
+       switch((sccr&SCCR_DFBRG11)>>11){
+               case 0:
+                       divider = 1;
+                       break;
+               case 1:
+                       divider = 4;
+                       break;
+               case 2:
+                       divider = 16;
+                       break;
+               case 3:
+                       divider = 64;
+                       break;
+       }
+       gd->brg_clk = gd->cpu_clk/divider;
+}
+
 #if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
 
 /*
@@ -181,8 +204,6 @@ unsigned long measure_gclk(void)
  */
 int get_clocks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uint immr = get_immr (0);       /* Return full IMMR contents */
        volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
        uint sccr = immap->im_clkrst.car_sccr;
@@ -223,6 +244,8 @@ int get_clocks (void)
                gd->bus_clk = gd->cpu_clk / 2;
        }
 
+       get_brgclk(sccr);
+
        return (0);
 }
 
@@ -238,8 +261,6 @@ static long init_pll_866 (long clk);
  */
 int get_clocks_866 (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *) CFG_IMMR;
        char              tmp[64];
        long              cpuclk = 0;
@@ -256,11 +277,14 @@ int get_clocks_866 (void)
        gd->cpu_clk = measure_gclk ();
 #endif
 
+       get_brgclk(immr->im_clkrst.car_sccr);
+
        /* if cpu clock <= 66 MHz then set bus division factor to 1,
         * otherwise set it to 2
         */
        sccr_reg = immr->im_clkrst.car_sccr;
        sccr_reg &= ~SCCR_EBDF11;
+
        if (gd->cpu_clk <= 66000000) {
                sccr_reg |= SCCR_EBDF00;        /* bus division factor = 1 */
                gd->bus_clk = gd->cpu_clk;
@@ -277,8 +301,6 @@ int get_clocks_866 (void)
  */
 int sdram_adjust_866 (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *) CFG_IMMR;
        long              mamr;
 
@@ -364,15 +386,14 @@ static long init_pll_866 (long clk)
 
 #endif /* CONFIG_8xx_CPUCLK_DEFAULT */
 
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
+    && !defined(CONFIG_TQM885D)
 /*
  * Adjust sdram refresh rate to actual CPU clock
  * and set timebase source according to actual CPU clock
  */
 int adjust_sdram_tbs_8xx (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *) CFG_IMMR;
        long              mamr;
        long              sccr;
@@ -390,6 +411,6 @@ int adjust_sdram_tbs_8xx (void)
 
        return (0);
 }
-#endif /* CONFIG_TQM8xxL/M, !TQM866M */
+#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
 
 /* ------------------------------------------------------------------------- */