#include <mpc8xx.h>
#include <asm/processor.h>
-#if !defined(CONFIG_TQM866M) || defined(CFG_MEASURE_CPUCLK)
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG)
#define PITC_SHIFT 16
#define PITR_SHIFT 16
* These strange values for the timing interval and prescaling are used
* because the formula for the CPU clock is:
*
- * CPU clock = count * (177 * (8192 / 58))
+ * CPU clock = count * (177 * (8192 / 58))
*
- * = count * 24999.7241
+ * = count * 24999.7241
*
- * which is very close to
+ * which is very close to
*
- * = count * 25000
+ * = count * 25000
*
* Since the count gives the CPU clock divided by 25000, we can get
* the CPU clock rounded to the nearest 0.1 MHz by
*
- * CPU clock = ((count + 2) / 4) * 100000;
+ * CPU clock = ((count + 2) / 4) * 100000;
*
* The rounding is important since the measurement is sometimes going
* to be high or low by 0.025 MHz, depending on exactly how the clocks
ulong timer2_val;
ulong msr_val;
-#ifdef CONFIG_MPC866_et_al
+#ifdef CFG_8XX_XIN
/* dont use OSCM, only use EXTCLK/512 */
immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
#else
*/
timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;
- timerp->cpmt_tcn2 = 0; /* reset state */
- timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */
+ timerp->cpmt_tcn2 = 0; /* reset state */
+ timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */
/*
* PIT setup:
/* spin until get exact count when we want to start */
while (immr->im_sit.sit_pitr > SPEED_PITC);
- timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */
+ timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */
while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
- timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */
+ timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */
/* re-enable external interrupts if they were on */
set_msr (msr_val);
timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
immr->im_sit.sit_piscr &= ~PISCR_PTE;
-#if defined(CONFIG_MPC866_et_al)
+#if defined(CFG_8XX_XIN)
/* not using OSCM, using XIN, so scale appropriately */
return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
#else
- return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
+ return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
#endif
}
#endif
-#if !defined(CONFIG_TQM866M)
+void get_brgclk(uint sccr)
+{
+ uint divider = 0;
+
+ switch((sccr&SCCR_DFBRG11)>>11){
+ case 0:
+ divider = 1;
+ break;
+ case 1:
+ divider = 4;
+ break;
+ case 2:
+ divider = 16;
+ break;
+ case 3:
+ divider = 64;
+ break;
+ }
+ gd->brg_clk = gd->cpu_clk/divider;
+}
+
+#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
/*
* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
*/
int get_clocks (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
-#ifndef CONFIG_8xx_GCLK_FREQ
- gd->cpu_clk = measure_gclk();
-#else /* CONFIG_8xx_GCLK_FREQ */
+ uint immr = get_immr (0); /* Return full IMMR contents */
+ volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
+ uint sccr = immap->im_clkrst.car_sccr;
/*
* If for some reason measuring the gclk frequency won't
* work, we return the hardwired value.
* (For example, the cogent CMA286-60 CPU module has no
* separate oscillator for PITRTCLK)
*/
-
+#if defined(CONFIG_8xx_GCLK_FREQ)
gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
-
+#elif defined(CONFIG_8xx_OSCLK)
+#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
+ uint pll = immap->im_clkrst.car_plprcr;
+ uint clk;
+
+ if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
+ clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) *
+ (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) /
+ (1<<PLPRCR_val(S));
+ } else {
+ clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1);
+ }
+ if (pll & PLPRCR_CSRC) { /* Low frequency division factor is used */
+ gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7));
+ } else { /* High frequency division factor is used */
+ gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7));
+ }
+#else
+ gd->cpu_clk = measure_gclk();
#endif /* CONFIG_8xx_GCLK_FREQ */
- if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) {
+ if ((sccr & SCCR_EBDF11) == 0) {
/* No Bus Divider active */
gd->bus_clk = gd->cpu_clk;
} else {
gd->bus_clk = gd->cpu_clk / 2;
}
+ get_brgclk(sccr);
+
return (0);
}
-#else /* CONFIG_MPC866_et_al */
+#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */
static long init_pll_866 (long clk);
/* This function sets up PLL (init_pll_866() is called) and
* fills gd->cpu_clk and gd->bus_clk according to the environment
- * variable 'cpuclk' or to CFG_866_CPUCLK_DEFAULT (if 'cpuclk'
+ * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
* contains invalid value).
- * This functions requires an MPC866 series CPU.
+ * This functions requires an MPC866 or newer series CPU.
*/
int get_clocks_866 (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
volatile immap_t *immr = (immap_t *) CFG_IMMR;
- char tmp[64];
- long cpuclk = 0;
+ char tmp[64];
+ long cpuclk = 0;
+ long sccr_reg;
if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
- if ((CFG_866_CPUCLK_MIN > cpuclk) || (CFG_866_CPUCLK_MAX < cpuclk))
- cpuclk = CFG_866_CPUCLK_DEFAULT;
+ if ((CFG_8xx_CPUCLK_MIN > cpuclk) || (CFG_8xx_CPUCLK_MAX < cpuclk))
+ cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
gd->cpu_clk = init_pll_866 (cpuclk);
#if defined(CFG_MEASURE_CPUCLK)
gd->cpu_clk = measure_gclk ();
#endif
- if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0)
+ get_brgclk(immr->im_clkrst.car_sccr);
+
+ /* if cpu clock <= 66 MHz then set bus division factor to 1,
+ * otherwise set it to 2
+ */
+ sccr_reg = immr->im_clkrst.car_sccr;
+ sccr_reg &= ~SCCR_EBDF11;
+
+ if (gd->cpu_clk <= 66000000) {
+ sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
gd->bus_clk = gd->cpu_clk;
- else
+ } else {
+ sccr_reg |= SCCR_EBDF01; /* bus division factor = 2 */
gd->bus_clk = gd->cpu_clk / 2;
+ }
+ immr->im_clkrst.car_sccr = sccr_reg;
return (0);
}
*/
int sdram_adjust_866 (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
volatile immap_t *immr = (immap_t *) CFG_IMMR;
- long mamr;
+ long mamr;
mamr = immr->im_memctl.memc_mamr;
mamr &= ~MAMR_PTA_MSK;
- mamr |= ((gd->cpu_clk / CFG_866_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+ mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
immr->im_memctl.memc_mamr = mamr;
return (0);
}
-/* Configure PLL for MPC866/859 CPU series
+/* Configure PLL for MPC866/859/885 CPU series
* PLL multiplication factor is set to the value nearest to the desired clk,
* assuming a oscclk of 10 MHz.
*/
extern void plprcr_write_866 (long);
volatile immap_t *immr = (immap_t *) CFG_IMMR;
- long n, plprcr;
- char mfi, mfn, mfd, s, pdf;
- long step_mfi, step_mfn;
+ long n, plprcr;
+ char mfi, mfn, mfd, s, pdf;
+ long step_mfi, step_mfn;
if (clk < 20000000) {
clk *= 2;
if (clk < 40000000) {
s = 2;
- step_mfi = CFG_866_OSCCLK / 4;
+ step_mfi = CONFIG_8xx_OSCLK / 4;
mfd = 7;
- step_mfn = CFG_866_OSCCLK / 30;
+ step_mfn = CONFIG_8xx_OSCLK / 30;
} else if (clk < 80000000) {
s = 1;
- step_mfi = CFG_866_OSCCLK / 2;
+ step_mfi = CONFIG_8xx_OSCLK / 2;
mfd = 14;
- step_mfn = CFG_866_OSCCLK / 30;
+ step_mfn = CONFIG_8xx_OSCLK / 30;
} else {
s = 0;
- step_mfi = CFG_866_OSCCLK;
+ step_mfi = CONFIG_8xx_OSCLK;
mfd = 29;
- step_mfn = CFG_866_OSCCLK / 30;
+ step_mfn = CONFIG_8xx_OSCLK / 30;
}
/* Calculate integer part of multiplication factor
return (n);
}
-#endif /* CONFIG_MPC866_et_al */
+#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
+
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
+ && !defined(CONFIG_TQM885D)
+/*
+ * Adjust sdram refresh rate to actual CPU clock
+ * and set timebase source according to actual CPU clock
+ */
+int adjust_sdram_tbs_8xx (void)
+{
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ long mamr;
+ long sccr;
+
+ mamr = immr->im_memctl.memc_mamr;
+ mamr &= ~MAMR_PTA_MSK;
+ mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+ immr->im_memctl.memc_mamr = mamr;
+
+ if (gd->cpu_clk < 67000000) {
+ sccr = immr->im_clkrst.car_sccr;
+ sccr |= SCCR_TBS;
+ immr->im_clkrst.car_sccr = sccr;
+ }
+
+ return (0);
+}
+#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
/* ------------------------------------------------------------------------- */
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