ppc/85xx: add cpu init config file for boot from NAND

[u-boot] / cpu / ppc4xx / 40x_spd_sdram.c

diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c
index b21b13e4936e81c6b4721fba7ccc1eb9e2839e64..83fa709da2dae636effcc069ec6386f162ca2859 100644 (file)
--- a/cpu/ppc4xx/40x_spd_sdram.c
+++ b/cpu/ppc4xx/40x_spd_sdram.c
@@ -52,12 +52,8 @@
 /*
  * Set default values
  */
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED  50000
-#endif
-
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE  0xFE
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED   50000
 #endif
 
 #define ONE_BILLION    1000000000
@@ -163,7 +159,7 @@ long int spd_sdram(int(read_spd)(uint addr))
                 * Make sure I2C controller is initialized
                 * before continuing.
                 */
-               i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+               i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
        }
 
        /* Make shure we are using SDRAM */
@@ -426,7 +422,7 @@ long int spd_sdram(int(read_spd)(uint addr))
         * program all the registers.
         * -------------------------------------------------------------------*/
 
-#define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+#define mtsdram0(reg, data)  mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
        /* disable memcontroller so updates work */
        mtsdram0( mem_mcopt1, 0 );