#include <ppc4xx.h>
#include <asm/mmu.h>
+#include "ecc.h"
+
#if defined(CONFIG_SPD_EEPROM) && \
(defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR))
/*
* Set default values
*/
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED 50000
-#endif
-
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE 0xFE
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED 50000
#endif
#define ONE_BILLION 1000000000
}
void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
-/*-----------------------------------------------------------------------------
- | Memory Controller Options 0
- +-----------------------------------------------------------------------------*/
-#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
-#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
-#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
-#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
-#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
-#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
-#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
-#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
-#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
-#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
-#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
-#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
-
-/*-----------------------------------------------------------------------------
- | Memory Controller Options 1
- +-----------------------------------------------------------------------------*/
-#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
-#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
-
-/*-----------------------------------------------------------------------------+
- | SDRAM DEVPOT Options
- +-----------------------------------------------------------------------------*/
-#define SDRAM_DEVOPT_DLL 0x80000000
-#define SDRAM_DEVOPT_DS 0x40000000
-
-/*-----------------------------------------------------------------------------+
- | SDRAM MCSTS Options
- +-----------------------------------------------------------------------------*/
-#define SDRAM_MCSTS_MRSC 0x80000000
-#define SDRAM_MCSTS_SRMS 0x40000000
-#define SDRAM_MCSTS_CIS 0x20000000
-
-/*-----------------------------------------------------------------------------
- | SDRAM Refresh Timer Register
- +-----------------------------------------------------------------------------*/
-#define SDRAM_RTR_RINT_MASK 0xFFFF0000
-#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
-#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
-
-/*-----------------------------------------------------------------------------+
- | SDRAM UABus Base Address Reg
- +-----------------------------------------------------------------------------*/
-#define SDRAM_UABBA_UBBA_MASK 0x0000000F
-
-/*-----------------------------------------------------------------------------+
- | Memory Bank 0-7 configuration
- +-----------------------------------------------------------------------------*/
-#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
-#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
-#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
-#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
-#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
-#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
-#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
-#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
-#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
-#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
-#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
-#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
-#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
-#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
-#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
-
-/*-----------------------------------------------------------------------------+
- | SDRAM TR0 Options
- +-----------------------------------------------------------------------------*/
-#define SDRAM_TR0_SDWR_MASK 0x80000000
-#define SDRAM_TR0_SDWR_2_CLK 0x00000000
-#define SDRAM_TR0_SDWR_3_CLK 0x80000000
-#define SDRAM_TR0_SDWD_MASK 0x40000000
-#define SDRAM_TR0_SDWD_0_CLK 0x00000000
-#define SDRAM_TR0_SDWD_1_CLK 0x40000000
-#define SDRAM_TR0_SDCL_MASK 0x01800000
-#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
-#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
-#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
-#define SDRAM_TR0_SDPA_MASK 0x000C0000
-#define SDRAM_TR0_SDPA_2_CLK 0x00040000
-#define SDRAM_TR0_SDPA_3_CLK 0x00080000
-#define SDRAM_TR0_SDPA_4_CLK 0x000C0000
-#define SDRAM_TR0_SDCP_MASK 0x00030000
-#define SDRAM_TR0_SDCP_2_CLK 0x00000000
-#define SDRAM_TR0_SDCP_3_CLK 0x00010000
-#define SDRAM_TR0_SDCP_4_CLK 0x00020000
-#define SDRAM_TR0_SDCP_5_CLK 0x00030000
-#define SDRAM_TR0_SDLD_MASK 0x0000C000
-#define SDRAM_TR0_SDLD_1_CLK 0x00000000
-#define SDRAM_TR0_SDLD_2_CLK 0x00004000
-#define SDRAM_TR0_SDRA_MASK 0x0000001C
-#define SDRAM_TR0_SDRA_6_CLK 0x00000000
-#define SDRAM_TR0_SDRA_7_CLK 0x00000004
-#define SDRAM_TR0_SDRA_8_CLK 0x00000008
-#define SDRAM_TR0_SDRA_9_CLK 0x0000000C
-#define SDRAM_TR0_SDRA_10_CLK 0x00000010
-#define SDRAM_TR0_SDRA_11_CLK 0x00000014
-#define SDRAM_TR0_SDRA_12_CLK 0x00000018
-#define SDRAM_TR0_SDRA_13_CLK 0x0000001C
-#define SDRAM_TR0_SDRD_MASK 0x00000003
-#define SDRAM_TR0_SDRD_2_CLK 0x00000001
-#define SDRAM_TR0_SDRD_3_CLK 0x00000002
-#define SDRAM_TR0_SDRD_4_CLK 0x00000003
-
-/*-----------------------------------------------------------------------------+
- | SDRAM TR1 Options
- +-----------------------------------------------------------------------------*/
-#define SDRAM_TR1_RDSS_MASK 0xC0000000
-#define SDRAM_TR1_RDSS_TR0 0x00000000
-#define SDRAM_TR1_RDSS_TR1 0x40000000
-#define SDRAM_TR1_RDSS_TR2 0x80000000
-#define SDRAM_TR1_RDSS_TR3 0xC0000000
-#define SDRAM_TR1_RDSL_MASK 0x00C00000
-#define SDRAM_TR1_RDSL_STAGE1 0x00000000
-#define SDRAM_TR1_RDSL_STAGE2 0x00400000
-#define SDRAM_TR1_RDSL_STAGE3 0x00800000
-#define SDRAM_TR1_RDCD_MASK 0x00000800
-#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
-#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
-#define SDRAM_TR1_RDCT_MASK 0x000001FF
-#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
-#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
-#define SDRAM_TR1_RDCT_MIN 0x00000000
-#define SDRAM_TR1_RDCT_MAX 0x000001FF
-
-/*-----------------------------------------------------------------------------+
- | SDRAM WDDCTR Options
- +-----------------------------------------------------------------------------*/
-#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
-#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
-#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
-#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
-#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
-
-/*-----------------------------------------------------------------------------+
- | SDRAM CLKTR Options
- +-----------------------------------------------------------------------------*/
-#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
-#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
-#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
-#define SDRAM_CLKTR_CLKP_180DEG 0x80000000
-#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
-
-/*-----------------------------------------------------------------------------+
- | SDRAM DLYCAL Options
- +-----------------------------------------------------------------------------*/
-#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
-#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
-#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
-
/*-----------------------------------------------------------------------------+
| General Definition
+-----------------------------------------------------------------------------*/
* memory.
*
* If at some time this restriction doesn't apply anymore, just define
- * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly.
*/
-#ifdef CFG_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_4xx_DCACHE
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
typedef struct bank_param BANKPARMS;
-#ifdef CFG_SIMULATE_SPD_EEPROM
-extern unsigned char cfg_simulate_spd_eeprom[128];
+#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
+extern const unsigned char cfg_simulate_spd_eeprom[128];
#endif
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
static unsigned char spd_read(uchar chip, uint addr);
static void get_spd_info(unsigned long *dimm_populated,
unsigned long num_dimm_banks);
static void program_tr1(void);
-#ifdef CONFIG_DDR_ECC
-static void program_ecc(unsigned long num_bytes);
-#endif
-
static unsigned long program_bxcr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
* Make sure I2C controller is initialized
* before continuing.
*/
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/*
* Read the SPD information using I2C interface. Check to see if the
*/
check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
/*
* Soft-reset SDRAM controller.
*/
- mtsdr(sdr_srst, SDR0_SRST_DMC);
- mtsdr(sdr_srst, 0x00000000);
+ mtsdr(SDR0_SRST, SDR0_SRST_DMC);
+ mtsdr(SDR0_SRST, 0x00000000);
#endif
/*
/*
* program SDRAM Clock Timing Register (SDRAM0_CLKTR)
*/
- mtsdram(mem_clktr, 0x40000000);
+ mtsdram(SDRAM0_CLKTR, 0x40000000);
/*
* delay to ensure 200 usec has elapsed
/*
* enable the memory controller
*/
- mfsdram(mem_cfg0, cfg0);
- mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
+ mfsdram(SDRAM0_CFG0, cfg0);
+ mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN);
/*
* wait for SDRAM_CFG0_DC_EN to complete
*/
while (1) {
- mfsdram(mem_mcsts, mcsts);
+ mfsdram(SDRAM0_MCSTS, mcsts);
if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
break;
}
/*
* If ecc is enabled, initialize the parity bits.
*/
- program_ecc(total_size);
+ ecc_init(CONFIG_SYS_SDRAM_BASE, total_size);
#endif
return total_size;
{
unsigned char data[2];
-#ifdef CFG_SIMULATE_SPD_EEPROM
- if (chip == CFG_SIMULATE_SPD_EEPROM) {
+#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
+ if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) {
/*
* Onboard spd eeprom requested -> simulate values
*/
return cfg_simulate_spd_eeprom[addr];
}
-#endif /* CFG_SIMULATE_SPD_EEPROM */
+#endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
if (i2c_probe(chip) == 0) {
if (i2c_read(chip, addr, 1, data, 1) == 0) {
/*
* get Memory Controller Options 0 data
*/
- mfsdram(mem_cfg0, cfg0);
+ mfsdram(SDRAM0_CFG0, cfg0);
/*
* clear bits
* Note: DCEN must be enabled after all DDR SDRAM controller
* configuration registers get initialized.
*/
- mtsdram(mem_cfg0, cfg0);
+ mtsdram(SDRAM0_CFG0, cfg0);
}
static void program_cfg1(unsigned long *dimm_populated,
unsigned long num_dimm_banks)
{
unsigned long cfg1;
- mfsdram(mem_cfg1, cfg1);
+ mfsdram(SDRAM0_CFG1, cfg1);
/*
* Self-refresh exit, disable PM
/*
* program Memory Controller Options 1
*/
- mtsdram(mem_cfg1, cfg1);
+ mtsdram(SDRAM0_CFG1, cfg1);
}
static void program_rtr(unsigned long *dimm_populated,
unsigned char refresh_rate_type;
unsigned long refresh_interval;
unsigned long sdram_rtr;
- PPC440_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
/*
* get the board info
/*
* program Refresh Timer Register (SDRAM0_RTR)
*/
- mtsdram(mem_rtr, sdram_rtr);
+ mtsdram(SDRAM0_RTR, sdram_rtr);
}
static void program_tr0(unsigned long *dimm_populated,
unsigned long tcyc_2_0_ns_x_10;
unsigned long tcyc_reg;
unsigned long bus_period_x_10;
- PPC440_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
unsigned long residue;
/*
/*
* get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
*/
- mfsdram(mem_tr0, tr0);
+ mfsdram(SDRAM0_TR0, tr0);
tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
}
debug("tr0: %x\n", tr0);
- mtsdram(mem_tr0, tr0);
+ mtsdram(SDRAM0_TR0, tr0);
}
static int short_mem_test(void)
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
- mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
- if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
+ mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2));
+ if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
/* Bank is enabled */
membase = (unsigned long*)
- (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
+ (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK);
/*
* Run the short memory test
unsigned char window_found;
unsigned char fail_found;
unsigned char pass_found;
- PPC440_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
/*
* get the board info
/*
* get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
*/
- mfsdram(mem_tr1, tr1);
+ mfsdram(SDRAM0_TR1, tr1);
tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
- mfsdram(mem_tr0, tr0);
+ mfsdram(SDRAM0_TR0, tr0);
if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
(sys_info.freqPLB > 100000000)) {
tr1 |= SDRAM_TR1_RDSS_TR2;
/*
* save CFG0 ECC setting to a temporary variable and turn ECC off
*/
- mfsdram(mem_cfg0, cfg0);
+ mfsdram(SDRAM0_CFG0, cfg0);
ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
+ mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
/*
* get the delay line calibration register value
*/
- mfsdram(mem_dlycal, dlycal);
+ mfsdram(SDRAM0_DLYCAL, dlycal);
dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
max_pass_length = 0;
/*
* Set the timing reg for the test.
*/
- mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
+ mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
if (short_mem_test()) {
if (fail_found == TRUE) {
/*
* restore the orignal ECC setting
*/
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
+ mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
/*
* set the SDRAM TR1 RDCD value
}
rdclt_average = ((max_start + max_end) >> 1);
- if (rdclt_average >= 0x60)
- while (1)
- ;
if (rdclt_average < 0) {
rdclt_average = 0;
/*
* program SDRAM Timing Register 1 TR1
*/
- mtsdram(mem_tr1, tr1);
+ mtsdram(SDRAM0_TR1, tr1);
}
static unsigned long program_bxcr(unsigned long *dimm_populated,
* Set the BxCR regs. First, wipe out the bank config registers.
*/
for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
- mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
- mtdcr(memcfgd, 0x00000000);
+ mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2));
+ mtdcr(SDRAM0_CFGDATA, 0x00000000);
bank_parms[bx_cr_num].bank_size_bytes = 0;
}
/*
* reset the bank_base address
*/
- bank_base_addr = CFG_SDRAM_BASE;
+ bank_base_addr = CONFIG_SYS_SDRAM_BASE;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
/* Set the SDRAM0_BxCR regs thanks to sort tables */
for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
- mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
- temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
+ mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2));
+ temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
bank_parms[sorted_bank_num[bx_cr_num]].cr;
- mtdcr(memcfgd, temp);
+ mtdcr(SDRAM0_CFGDATA, temp);
bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
}
return(bank_base_addr);
}
-
-#ifdef CONFIG_DDR_ECC
-static void program_ecc(unsigned long num_bytes)
-{
- unsigned long bank_base_addr;
- unsigned long current_address;
- unsigned long end_address;
- unsigned long address_increment;
- unsigned long cfg0;
-
- /*
- * get Memory Controller Options 0 data
- */
- mfsdram(mem_cfg0, cfg0);
-
- /*
- * reset the bank_base address
- */
- bank_base_addr = CFG_SDRAM_BASE;
-
- if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN);
-
- if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32)
- address_increment = 4;
- else
- address_increment = 8;
-
- current_address = (unsigned long)(bank_base_addr);
- end_address = (unsigned long)(bank_base_addr) + num_bytes;
-
- while (current_address < end_address) {
- *((unsigned long*)current_address) = 0x00000000;
- current_address += address_increment;
- }
-
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
- SDRAM_CFG0_MCHK_CHK);
- }
-}
-#endif /* CONFIG_DDR_ECC */
#endif /* CONFIG_SPD_EEPROM */