Merge git://www.denx.de/git/u-boot

[u-boot] / cpu / ppc4xx / 44x_spd_ddr2.c

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 626b3e69bd9b5b06cd58d3fe7d9f7b5eb2061c84..5fef27b984d57073b74b71e825b389cfbd69d46e 100644 (file)
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -58,8 +58,8 @@
 #define SDRAM_DDR2     2
 #define SDRAM_NONE     0
 
-#define MAXDIMMS       2
-#define MAXRANKS       4
+#define MAXDIMMS       2
+#define MAXRANKS       4
 #define MAXBXCF                4
 #define MAX_SPD_BYTES  256   /* Max number of bytes on the DIMM's SPD EEPROM */
 
@@ -154,7 +154,7 @@ typedef enum ddr_cas_id {
  * Prototypes
  *-----------------------------------------------------------------------------*/
 static unsigned long sdram_memsize(void);
-void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 static void get_spd_info(unsigned long *dimm_populated,
                         unsigned char *iic0_dimm_addr,
                         unsigned long num_dimm_banks);
@@ -538,7 +538,7 @@ long int initdram(int board_type)
        dram_size = sdram_memsize();
 
        /* and program tlb entries for this size (dynamic) */
-       program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
+       program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 
        /*------------------------------------------------------------------
         * DQS calibration.