TQM85xx: Support for Intel 82527 compatible CAN controller

[u-boot] / cpu / ppc4xx / 44x_spd_ddr2.c

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 9e722b998453faa18c56dcbe9661126ba21f69f1..ec76b718bccb1f2b86215259bc16f20f80f9d8fc 100644 (file)
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -1,7 +1,10 @@
 /*
  * cpu/ppc4xx/44x_spd_ddr2.c
  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
- * DDR2 controller (non Denali Core). Those are 440SP/SPe.
+ * DDR2 controller (non Denali Core). Those currently are:
+ *
+ * 405:                405EX
+ * 440/460:    440SP/440SPe/460EX/460GT
  *
  * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
@@ -40,6 +43,7 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <asm/cache.h>
 
 #if defined(CONFIG_SPD_EEPROM) &&                              \
        (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
@@ -237,7 +241,6 @@ static void DQS_calibration_process(void);
 static void ppc440sp_sdram_register_dump(void);
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 void dcbz_area(u32 start_address, u32 num_bytes);
-void dflush(void);
 
 static u32 mfdcr_any(u32 dcr)
 {
@@ -2078,7 +2081,7 @@ static void program_bxcf(unsigned long *dimm_populated,
                                if (num_banks == 4)
                                        ind = 0;
                                else
-                                       ind = 5;
+                                       ind = 5 << 8;
                                switch (num_col_addr) {
                                case 0x08:
                                        mode |= (SDRAM_BXCF_M_AM_0 + ind);
@@ -2355,7 +2358,8 @@ static void program_ecc_addr(unsigned long start_address,
                } else {
                        /* ECC bit set method for cached memory */
                        dcbz_area(start_address, num_bytes);
-                       dflush();
+                       /* Write modified dcache lines back to memory */
+                       clean_dcache_range(start_address, start_address + num_bytes);
                }
 
                blank_string(strlen(str));