#define LAST_EMAC_NUM 1
#endif
+/* normal boards start with EMAC0 */
+#if !defined(CONFIG_EMAC_NR_START)
+#define CONFIG_EMAC_NR_START 0
+#endif
+
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
bis->bi_phymode[3] = BI_PHYMODE_ZMII;
break;
case 2:
- zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
- zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
- zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
- zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
+ zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
+ zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
+ zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
+ zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
bis->bi_phymode[0] = BI_PHYMODE_ZMII;
bis->bi_phymode[1] = BI_PHYMODE_ZMII;
bis->bi_phymode[2] = BI_PHYMODE_ZMII;
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
unsigned long zmiifer=0x0;
+ unsigned long pfc1;
- /*
- * Right now only 2*RGMII is supported. Please extend when needed.
- * sr - 2006-08-29
- */
- switch (1) {
- case 0:
+ mfsdr(sdr_pfc1, pfc1);
+ pfc1 &= SDR0_PFC1_SELECT_MASK;
+
+ switch (pfc1) {
+ case SDR0_PFC1_SELECT_CONFIG_2:
/* 1 x GMII port */
out32 (ZMII_FER, 0x00);
out32 (RGMII_FER, 0x00000037);
bis->bi_phymode[0] = BI_PHYMODE_GMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
- case 1:
+ case SDR0_PFC1_SELECT_CONFIG_4:
/* 2 x RGMII ports */
out32 (ZMII_FER, 0x00);
out32 (RGMII_FER, 0x00000055);
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break;
- case 2:
+ case SDR0_PFC1_SELECT_CONFIG_6:
/* 2 x SMII ports */
-
+ out32 (ZMII_FER,
+ ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
+ ((ZMII_FER_SMII) << ZMII_FER_V(1)));
+ out32 (RGMII_FER, 0x00000000);
+ bis->bi_phymode[0] = BI_PHYMODE_SMII;
+ bis->bi_phymode[1] = BI_PHYMODE_SMII;
+ break;
+ case SDR0_PFC1_SELECT_CONFIG_1_2:
+ /* only 1 x MII supported */
+ out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
+ out32 (RGMII_FER, 0x00000000);
+ bis->bi_phymode[0] = BI_PHYMODE_MII;
+ bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
default:
break;
#else
if ((devnum == 0) || (devnum == 1)) {
out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
- }
- else { /* ((devnum == 2) || (devnum == 3)) */
+ } else { /* ((devnum == 2) || (devnum == 3)) */
out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
(RGMII_FER_RGMII << RGMII_FER_V (3))));
* otherwise, just check the speeds & feeds
*/
if (hw_p->first_init == 0) {
-#if defined(CONFIG_88E1111_CLK_DELAY)
- /*
- * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs
- * the "RGMII transmit timing control" and "RGMII receive
- * timing control" bits set, so that Gbit communication works
- * without problems.
- * Also set the "Transmitter disable" to 1 to enable the
- * transmitter.
- * After setting these bits a soft-reset must occur for this
- * change to become active.
- */
- miiphy_read (dev->name, reg, 0x14, ®_short);
- reg_short |= (1 << 7) | (1 << 1) | (1 << 0);
- miiphy_write (dev->name, reg, 0x14, reg_short);
-#endif
-#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */
+#if defined(CONFIG_M88E1111_PHY)
miiphy_write (dev->name, reg, 0x14, 0x0ce3);
miiphy_write (dev->name, reg, 0x18, 0x4101);
miiphy_write (dev->name, reg, 0x09, 0x0e00);
/* end Vitesse/Cicada errata */
}
#endif
+
+#if defined(CONFIG_ET1011C_PHY)
+ /*
+ * Agere ET1011c PHY needs to have an extended register whacked
+ * for RGMII mode.
+ */
+ if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
+ miiphy_read (dev->name, reg, 0x16, ®_short);
+ reg_short &= ~(0x7);
+ reg_short |= 0x6; /* RGMII DLL Delay*/
+ miiphy_write (dev->name, reg, 0x16, reg_short);
+
+ miiphy_read (dev->name, reg, 0x17, ®_short);
+ reg_short &= ~(0x40);
+ miiphy_write (dev->name, reg, 0x17, reg_short);
+
+ miiphy_write(dev->name, reg, 0x1c, 0x74f0);
+ }
+#endif
+
#endif
/* Start/Restart autonegotiation */
phy_setup_aneg (dev->name, reg);
if (hw_p->print_speed) {
hw_p->print_speed = 0;
- printf ("ENET Speed is %d Mbps - %s duplex connection\n",
- (int) speed, (duplex == HALF) ? "HALF" : "FULL");
+ printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
+ (int) speed, (duplex == HALF) ? "HALF" : "FULL",
+ hw_p->devnum);
}
#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
hw_p->rx_ready[i] = -1;
#if 0
- printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
+ printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr);
#endif
}
}
}
mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
+#if defined(CONFIG_405EZ)
+ mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
+#endif /* defined(CONFIG_405EZ) */
}
while (serviced);
if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
|| (loop_count >= NUM_RX_BUFF))
break;
+
loop_count++;
- hw_p->rx_slot++;
- if (NUM_RX_BUFF == hw_p->rx_slot)
- hw_p->rx_slot = 0;
handled++;
data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
if (data_len) {
if (NUM_RX_BUFF == hw_p->rx_i_index)
hw_p->rx_i_index = 0;
+ hw_p->rx_slot++;
+ if (NUM_RX_BUFF == hw_p->rx_slot)
+ hw_p->rx_slot = 0;
+
/* AS.HARNOIS
* free receive buffer only when
* buffer has been handled (eth_rx)
struct eth_device *dev;
int eth_num = 0;
EMAC_4XX_HW_PST hw = NULL;
+ u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
+ u32 hw_addr[4];
#if defined(CONFIG_440GX)
unsigned long pfc1;
pfc1 |= 0x01200000;
mtsdr (sdr_pfc1, pfc1);
#endif
- /* set phy num and mode */
- bis->bi_phynum[0] = CONFIG_PHY_ADDR;
- bis->bi_phymode[0] = 0;
-#if defined(CONFIG_PHY1_ADDR)
- bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
- bis->bi_phymode[1] = 0;
-#endif
-#if defined(CONFIG_440GX)
- bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
- bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
- bis->bi_phymode[2] = 2;
- bis->bi_phymode[3] = 2;
-
- ppc_4xx_eth_setup_bridge(0, bis);
-#endif
+ /* first clear all mac-addresses */
+ for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
+ memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
-
- /* See if we can actually bring up the interface, otherwise, skip it */
switch (eth_num) {
default: /* fall through */
case 0:
- if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
- bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
- continue;
- }
+ memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+ bis->bi_enetaddr, 6);
+ hw_addr[eth_num] = 0x0;
break;
#ifdef CONFIG_HAS_ETH1
case 1:
- if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
- bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
- continue;
- }
+ memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+ bis->bi_enet1addr, 6);
+ hw_addr[eth_num] = 0x100;
break;
#endif
#ifdef CONFIG_HAS_ETH2
case 2:
- if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
- bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
- continue;
- }
+ memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+ bis->bi_enet2addr, 6);
+ hw_addr[eth_num] = 0x400;
break;
#endif
#ifdef CONFIG_HAS_ETH3
case 3:
- if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
- bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
- continue;
- }
+ memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+ bis->bi_enet3addr, 6);
+ hw_addr[eth_num] = 0x600;
break;
#endif
}
+ }
+
+ /* set phy num and mode */
+ bis->bi_phynum[0] = CONFIG_PHY_ADDR;
+ bis->bi_phymode[0] = 0;
+
+#if defined(CONFIG_PHY1_ADDR)
+ bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
+ bis->bi_phymode[1] = 0;
+#endif
+#if defined(CONFIG_440GX)
+ bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
+ bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
+ bis->bi_phymode[2] = 2;
+ bis->bi_phymode[3] = 2;
+
+ ppc_4xx_eth_setup_bridge(0, bis);
+#endif
+
+ for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
+ /*
+ * See if we can actually bring up the interface,
+ * otherwise, skip it
+ */
+ if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
+ bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
+ continue;
+ }
/* Allocate device structure */
dev = (struct eth_device *) malloc (sizeof (*dev));
}
memset(hw, 0, sizeof(*hw));
- switch (eth_num) {
- default: /* fall through */
- case 0:
- hw->hw_addr = 0;
- memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
- break;
-#ifdef CONFIG_HAS_ETH1
- case 1:
- hw->hw_addr = 0x100;
- memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
- break;
-#endif
-#ifdef CONFIG_HAS_ETH2
- case 2:
- hw->hw_addr = 0x400;
- memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
- break;
-#endif
-#ifdef CONFIG_HAS_ETH3
- case 3:
- hw->hw_addr = 0x600;
- memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
- break;
-#endif
- }
-
+ hw->hw_addr = hw_addr[eth_num];
+ memcpy (dev->enetaddr, ethaddr[eth_num], 6);
hw->devnum = eth_num;
hw->print_speed = 1;
- sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
+ sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
dev->priv = (void *) hw;
dev->init = ppc_4xx_eth_init;
dev->halt = ppc_4xx_eth_halt;
return (1);
}
-
#if !defined(CONFIG_NET_MULTI)
void eth_halt (void) {
if (emac0_dev) {
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