Merge 'next' branch

[u-boot] / cpu / ppc4xx / 4xx_ibm_ddr2_autocalib.c

diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 83b9883a7726efa896300848fb4db4699f51b2dd..1e3e20df2e8fed402db7b421957070a83fec09f3 100644 (file)
--- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -53,11 +53,11 @@
 #define MAXBXCF                        4
 #define SDRAM_RXBAS_SHIFT_1M   20
 
-#if defined(CFG_DECREMENT_PATTERNS)
+#if defined(CONFIG_SYS_DECREMENT_PATTERNS)
 #define NUMMEMTESTS            24
 #else
 #define NUMMEMTESTS            8
-#endif /* CFG_DECREMENT_PATTERNS */
+#endif /* CONFIG_SYS_DECREMENT_PATTERNS */
 #define NUMLOOPS               1       /* configure as you deem approporiate */
 #define NUMMEMWORDS            16
 
@@ -174,6 +174,23 @@ static inline void ecc_clear_status_reg(void)
 #endif
 }
 
+/*
+ * Reset and relock memory DLL after SDRAM_CLKTR change
+ */
+static inline void relock_memory_DLL(void)
+{
+       u32 reg;
+
+       mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE);
+
+       do {
+               mfsdram(SDRAM_MCSTAT, reg);
+       } while (!(reg & SDRAM_MCSTAT_MIC_COMP));
+
+       mfsdram(SDRAM_MCOPT2, reg);
+       mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE);
+}
+
 static int ecc_check_status_reg(void)
 {
        u32 ecc_status;
@@ -237,7 +254,7 @@ static int short_mem_test(u32 *base_address)
                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55},
 
-#if defined(CFG_DECREMENT_PATTERNS)
+#if defined(CONFIG_SYS_DECREMENT_PATTERNS)
        /* 8 */ {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
                 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
                 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
@@ -302,7 +319,7 @@ static int short_mem_test(u32 *base_address)
                 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
                 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
                 0xfff0fff0, 0xfff0fffe, 0xfff0fff0, 0xfff0fff0},
-#endif /* CFG_DECREMENT_PATTERNS */
+#endif /* CONFIG_SYS_DECREMENT_PATTERNS */
                                                                 };
 
        mfsdram(SDRAM_MCOPT1, ecc_mode);
@@ -981,6 +998,8 @@ u32 DQS_autocalibration(void)
 
                mtsdram(SDRAM_CLKTR, clkp << 30);
 
+               relock_memory_DLL();
+
                putc('\b');
                putc(slash[loopi++ % 8]);
 
@@ -1170,6 +1189,8 @@ u32 DQS_autocalibration(void)
 
                mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30);
 
+               relock_memory_DLL();
+
                mfsdram(SDRAM_RQDC, rqdc_reg);
                rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
                mtsdram(SDRAM_RQDC, rqdc_reg |