]> git.sur5r.net Git - u-boot/blobdiff - cpu/ppc4xx/4xx_pcie.c
ppc4xx: Fix PCIE PLL lock on 440SPe Yucca board
[u-boot] / cpu / ppc4xx / 4xx_pcie.c
index 58d96bb5af3c035cea802ec86f40a2b02b447775..e880c288e1f2e2e01e700034639ab607d4b3110d 100644 (file)
@@ -374,28 +374,35 @@ int ppc4xx_init_pcie(void)
        /* Set PLL clock receiver to LVPECL */
        SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
 
-       if (check_error())
+       if (check_error()) {
+               printf("ERROR: failed to set PCIe reference clock receiver --"
+                       "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1));
+
                return -1;
+       }
+
+       /* Did resistance calibration work? */
+       if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) {
+               printf("ERROR: PCIe resistance calibration failed --"
+                       "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2));
 
-       if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
-       {
-               printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
-                      SDR_READ(PESDR0_PLLLCT2));
                return -1;
        }
        /* De-assert reset of PCIe PLL, wait for lock */
        SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
-       udelay(3);
+       udelay(300);    /* 300 uS is maximum time lock should take */
 
        while (time_out) {
                if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
                        time_out--;
-                       udelay(1);
+                       udelay(20);     /* Wait 20 uS more if needed */
                } else
                        break;
        }
        if (!time_out) {
-               printf("PCIE: VCO output not locked\n");
+               printf("ERROR: PCIe PLL VCO output not locked to ref clock --"
+                       "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3));
+
                return -1;
        }
        return 0;
@@ -1028,10 +1035,10 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 #endif
        }
 
-       /* Set up 16GB inbound memory window at 0 */
+       /* Set up 4GB inbound memory window at 0 */
        out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
        out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
-       out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
+       out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff);
        out_le32(mbase + PECFG_BAR0LMPA, 0);
 
        out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);