Merge with /home/stefan/git/u-boot/denx

[u-boot] / cpu / ppc4xx / cpu.c

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index d9b5d32c90cce95d00a5f23c8519366a39e3c321..faa525750486edae41741d20fe9cb26f6bc92516 100644 (file)
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -41,6 +41,9 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
+#if defined(CONFIG_BOARD_RESET)
+void board_reset(void);
+#endif
 
 #if defined(CONFIG_440)
 #define FREQ_EBC               (sys_info.freqEPB)
@@ -48,7 +51,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define FREQ_EBC               (sys_info.freqPLB / sys_info.pllExtBusDiv)
 #endif
 
-#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_405GP) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 #define PCI_ASYNC
 
@@ -58,7 +63,8 @@ int pci_async_enabled(void)
        return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
 #endif
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
        unsigned long val;
 
        mfsdr(sdr_sdstp1, val);
@@ -82,7 +88,10 @@ int pci_arbiter_enabled(void)
        return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
        unsigned long val;
 
        mfsdr(sdr_sdstp1, val);
@@ -91,8 +100,10 @@ int pci_arbiter_enabled(void)
 }
 #endif
 
-#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-       defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 
 #define I2C_BOOTROM
 
@@ -100,15 +111,75 @@ int i2c_bootrom_enabled(void)
 {
 #if defined(CONFIG_405EP)
        return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
-#endif
-
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#else
        unsigned long val;
 
        mfsdr(sdr_sdcs, val);
        return (val & SDR0_SDCS_SDD);
 #endif
 }
+
+#if defined(CONFIG_440GX)
+#define SDR0_PINSTP_SHIFT      29
+static char *bootstrap_str[] = {
+       "EBC (16 bits)",
+       "EBC (8 bits)",
+       "EBC (32 bits)",
+       "EBC (8 bits)",
+       "PCI",
+       "I2C (Addr 0x54)",
+       "Reserved",
+       "I2C (Addr 0x50)",
+};
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define SDR0_PINSTP_SHIFT      30
+static char *bootstrap_str[] = {
+       "EBC (8 bits)",
+       "PCI",
+       "I2C (Addr 0x54)",
+       "I2C (Addr 0x50)",
+};
+#endif
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define SDR0_PINSTP_SHIFT      29
+static char *bootstrap_str[] = {
+       "EBC (8 bits)",
+       "PCI",
+       "NAND (8 bits)",
+       "EBC (16 bits)",
+       "EBC (16 bits)",
+       "I2C (Addr 0x54)",
+       "PCI",
+       "I2C (Addr 0x52)",
+};
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_PINSTP_SHIFT      29
+static char *bootstrap_str[] = {
+       "EBC (8 bits)",
+       "EBC (16 bits)",
+       "EBC (16 bits)",
+       "NAND (8 bits)",
+       "PCI",
+       "I2C (Addr 0x54)",
+       "PCI",
+       "I2C (Addr 0x52)",
+};
+#endif
+
+#if defined(SDR0_PINSTP_SHIFT)
+static int bootstrap_option(void)
+{
+       unsigned long val;
+
+       mfsdr(sdr_pinstp, val);
+       return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
+}
+#endif /* SDR0_PINSTP_SHIFT */
 #endif
 
 
@@ -125,6 +196,7 @@ int checkcpu (void)
        char buf[32];
 
 #if !defined(CONFIG_IOP480)
+       char addstr[64] = "";
        sys_info_t sys_info;
 
        puts ("CPU:   ");
@@ -240,6 +312,26 @@ int checkcpu (void)
 #endif /* CONFIG_440GR */
 #endif /* CONFIG_440 */
 
+       case PVR_440EPX1_RA:
+               puts("EPx Rev. A");
+               strcpy(addstr, "Security/Kasumi support");
+               break;
+
+       case PVR_440EPX2_RA:
+               puts("EPx Rev. A");
+               strcpy(addstr, "No Security/Kasumi support");
+               break;
+
+       case PVR_440GRX1_RA:
+               puts("GRx Rev. A");
+               strcpy(addstr, "Security/Kasumi support");
+               break;
+
+       case PVR_440GRX2_RA:
+               puts("GRx Rev. A");
+               strcpy(addstr, "No Security/Kasumi support");
+               break;
+
        case PVR_440SP_RA:
                puts("SP Rev. A");
                break;
@@ -248,6 +340,14 @@ int checkcpu (void)
                puts("SP Rev. B");
                break;
 
+       case PVR_440SPe_RA:
+               puts("SPe Rev. A");
+               break;
+
+       case PVR_440SPe_RB:
+               puts("SPe Rev. B");
+               break;
+
        default:
                printf (" UNKNOWN (PVR=%08x)", pvr);
                break;
@@ -258,9 +358,16 @@ int checkcpu (void)
               sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
               FREQ_EBC / 1000000);
 
+       if (addstr[0] != 0)
+               printf("       %s\n", addstr);
+
 #if defined(I2C_BOOTROM)
        printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
-#endif
+#if defined(SDR0_PINSTP_SHIFT)
+       printf ("       Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
+       printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
+#endif /* SDR0_PINSTP_SHIFT */
+#endif /* I2C_BOOTROM */
 
 #if defined(CONFIG_PCI)
        printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
@@ -303,28 +410,31 @@ int checkcpu (void)
        return 0;
 }
 
+#if defined (CONFIG_440SPE)
+int ppc440spe_revB() {
+       unsigned int pvr;
+
+       pvr = get_pvr();
+       if (pvr == PVR_440SPe_RB)
+               return 1;
+       else
+               return 0;
+}
+#endif
 
 /* ------------------------------------------------------------------------- */
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
-       /*give reset to BCSR*/
-       *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
-
+#if defined(CONFIG_BOARD_RESET)
+       board_reset();
 #else
-
        /*
         * Initiate system reset in debug control register DBCR
         */
-       __asm__ __volatile__("lis   3, 0x3000" ::: "r3");
-#if defined(CONFIG_440)
-       __asm__ __volatile__("mtspr 0x134, 3");
-#else
-       __asm__ __volatile__("mtspr 0x3f2, 3");
-#endif
+       mtspr(dbcr0, 0x30000000);
+#endif /* defined(CONFIG_BOARD_RESET) */
 
-#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
        return 1;
 }