ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT

[u-boot] / cpu / ppc4xx / ecc.h

diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h
index 67c3bff878ef3d0fb18338084bdc37d28d62c121..b2588919ebec0e6e9f8b7b78babe906dee76d18f 100644 (file)
--- a/cpu/ppc4xx/ecc.h
+++ b/cpu/ppc4xx/ecc.h
@@ -2,7 +2,7 @@
  *    Copyright (c) 2008 Nuovation System Designs, LLC
  *     Grant Erickson <gerickson@nuovations.com>
  *
- *    Copyright (c) 2007 DENX Software Engineering, GmbH
+ *    Copyright (c) 2007-2009 DENX Software Engineering, GmbH
  *     Stefan Roese <sr@denx.de>
  *
  *    See file CREDITS for list of people who contributed to this
@@ -25,18 +25,13 @@
  *
  *    Description:
  *     This file implements ECC initialization for PowerPC processors
- *     using the SDRAM DDR2 controller, including the 405EX(r),
- *     440SP(E), 460EX and 460GT.
+ *     using the IBM SDRAM DDR1 & DDR2 controller.
  *
  */
 
 #ifndef _ECC_H_
 #define _ECC_H_
 
-#if !defined(CONFIG_SYS_ECC_PATTERN)
-#define        CONFIG_SYS_ECC_PATTERN  0x00000000
-#endif /* !defined(CONFIG_SYS_ECC_PATTERN) */
-
 /*
  * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
  * compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
@@ -46,24 +41,35 @@
 
 /* For 440GP/GX/EP/GR */
 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
-#define SDRAM_ECC_CFG          SDRAM_CFG0
-#define SDRAM_ECC_CFG_MCHK_MASK        SDRAM_CFG0_MCHK_MASK
-#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_CFG0_MCHK_GEN
-#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_CFG0_MCHK_CHK
-#define SDRAM_ECC_CFG_DMWD_MASK        SDRAM_CFG0_DMWD_MASK
-#define SDRAM_ECC_CFG_DMWD_32  SDRAM_CFG0_DMWD_32
-#endif
+#define SDRAM_MCOPT1           SDRAM_CFG0
+#define SDRAM_MCOPT1_MCHK_MASK SDRAM_CFG0_MCHK_MASK
+#define SDRAM_MCOPT1_MCHK_NON  SDRAM_CFG0_MCHK_NON
+#define SDRAM_MCOPT1_MCHK_GEN  SDRAM_CFG0_MCHK_GEN
+#define SDRAM_MCOPT1_MCHK_CHK  SDRAM_CFG0_MCHK_CHK
+#define SDRAM_MCOPT1_MCHK_CHK_REP SDRAM_CFG0_MCHK_CHK
+#define SDRAM_MCOPT1_DMWD_MASK SDRAM_CFG0_DMWD_MASK
+#define SDRAM_MCOPT1_DMWD_32   SDRAM_CFG0_DMWD_32
+
+#define SDRAM_MCSTAT           SDRAM0_MCSTS
+#define SDRAM_MCSTAT_IDLE_MASK SDRAM_MCSTS_CIS
+#define SDRAM_MCSTAT_IDLE_NOT  SDRAM_MCSTS_IDLE_NOT
 
-/* For 405EX/440SP/SPe/460EX/GT */
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
-#define SDRAM_ECC_CFG          SDRAM_MCOPT1
-#define SDRAM_ECC_CFG_MCHK_MASK        SDRAM_MCOPT1_MCHK_MASK
-#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_MCOPT1_MCHK_GEN
-#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_MCOPT1_MCHK_CHK
-#define SDRAM_ECC_CFG_DMWD_MASK        SDRAM_MCOPT1_DMWD_MASK
-#define SDRAM_ECC_CFG_DMWD_32  SDRAM_MCOPT1_DMWD_32
+#define SDRAM_ECCES            SDRAM0_ECCESR
 #endif
 
-extern void ecc_init(unsigned long * const start, unsigned long size);
+void ecc_init(unsigned long * const start, unsigned long size);
+void do_program_ecc(unsigned long tlb_word2_i_value);
+
+static void inline blank_string(int size)
+{
+       int i;
+
+       for (i = 0; i < size; i++)
+               putc('\b');
+       for (i = 0; i < size; i++)
+               putc(' ');
+       for (i = 0; i < size; i++)
+               putc('\b');
+}
 
 #endif /* _ECC_H_ */