#include <commproc.h>
#include "vecnum.h"
+DECLARE_GLOBAL_DATA_PTR;
+
/****************************************************************************/
/*
void uic1_interrupt( void * parms); /* UIC1 handler */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
static struct irq_action irq_vecs2[32]; /* For UIC2 */
void uic0_interrupt( void * parms); /* UIC0 handler */
void uic2_interrupt( void * parms); /* UIC2 handler */
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#endif /* CONFIG_440 */
int interrupt_init_cpu (unsigned *decrementer_count)
{
- DECLARE_GLOBAL_DATA_PTR;
-
int vec;
unsigned long val;
irq_vecs1[vec].handler = NULL;
irq_vecs1[vec].arg = NULL;
irq_vecs1[vec].count = 0;
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
irq_vecs2[vec].handler = NULL;
irq_vecs2[vec].arg = NULL;
irq_vecs2[vec].count = 0;
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#endif
}
mtspr( dec, 0 ); /* Prevent exception after TSR clear*/
mtspr( decar, 0 ); /* clear reload */
mtspr( tsr, 0x08000000 ); /* clear DEC status */
- val = gd->bd->bi_intfreq/100; /* 10 msec */
+ val = gd->bd->bi_intfreq/1000; /* 1 msec */
mtspr( decar, val ); /* Set auto-reload value */
mtspr( dec, val ); /* Set inital val */
#else
set_evpr(0x00000000);
#if defined(CONFIG_440)
-#if !defined(CONFIG_440_GX)
+#if !defined(CONFIG_440GX)
/* Install the UIC1 handlers */
irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
#endif
#endif
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
+ /* Take the GX out of compatibility mode
+ * Travis Sawyer, 9 Mar 2004
+ * NOTE: 440gx user manual inconsistency here
+ * Compatibility mode and Ethernet Clock select are not
+ * correct in the manual
+ */
+ mfsdr(sdr_mfr, val);
+ val &= ~0x10000000;
+ mtsdr(sdr_mfr,val);
+
/* Enable UIC interrupts via UIC Base Enable Register */
- mtdcr(uicb0er, UICB0_ALL);
- mtdcr(uicb0cr, UICB0_ALL);
+ mtdcr(uicb0sr, UICB0_ALL);
+ mtdcr(uicb0er, 0x54000000);
+ /* None are critical */
+ mtdcr(uicb0cr, 0);
#endif
return (0);
/*
* Handle external interrupts
*/
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
void external_interrupt(struct pt_regs *regs)
{
ulong uic_msr;
/* 440 GX uses base uic register */
uic_msr = mfdcr(uicb0msr);
- uic0_interrupt(0);
- uic1_interrupt(0);
- uic2_interrupt(0);
+ if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) )
+ uic0_interrupt(0);
- mtdcr(uicb0sr, UICB0_ALL);
+ if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
+ uic1_interrupt(0);
+
+ if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
+ uic2_interrupt(0);
+
+ mtdcr(uicb0sr, uic_msr);
return;
-} /* external_interrupt CONFIG_440_GX */
+} /* external_interrupt CONFIG_440GX */
#else
}
#endif
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
/* Handler for UIC0 interrupt */
void uic0_interrupt( void * parms)
{
}
}
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#if defined(CONFIG_440)
/* Handler for UIC1 interrupt */
}
#endif /* defined(CONFIG_440) */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
/* Handler for UIC1 interrupt */
void uic2_interrupt( void * parms)
{
vec++;
}
}
-#endif /* defined(CONFIG_440_GX) */
+#endif /* defined(CONFIG_440GX) */
/****************************************************************************/
int i = vec;
#if defined(CONFIG_440)
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64)) {
i = vec - 32;
irqa = irq_vecs1;
i = vec - 64;
irqa = irq_vecs2;
}
-#else /* CONFIG_440_GX */
+#else /* CONFIG_440GX */
if (vec > 31) {
i = vec - 32;
irqa = irq_vecs1;
}
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#endif /* CONFIG_440 */
- if (irqa[i].handler != NULL) {
+ /*
+ * print warning when replacing with a different irq vector
+ */
+ if ((irqa[i].handler != NULL) && (irqa[i].handler != handler)) {
printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
vec, (uint) handler, (uint) irqa[i].handler);
}
irqa[i].arg = arg;
#if defined(CONFIG_440)
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
else if (vec > 63)
mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i));
else
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
if (vec > 31)
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
else
int i = vec;
#if defined(CONFIG_440)
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64)) {
irqa = irq_vecs1;
i = vec - 32;
irqa = irq_vecs2;
i = vec - 64;
}
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
if (vec > 31) {
irqa = irq_vecs1;
i = vec - 32;
#endif
#if defined(CONFIG_440)
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
else if (vec > 63)
mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i));
else
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
if (vec > 31)
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
else
printf("\n");
#endif
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
printf ("\nUIC 2\n");
printf ("Nr Routine Arg Count\n");