TQM85xx: Support for Intel 82527 compatible CAN controller

[u-boot] / cpu / ppc4xx / kgdb.S

diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S
index 78681cd1d29f4f2c4b346c57540e591d181736c6..4227a4c15b6b3b13a5fed98f6280bafdf695e1c9 100644 (file)
--- a/cpu/ppc4xx/kgdb.S
+++ b/cpu/ppc4xx/kgdb.S
@@ -34,7 +34,7 @@
 #include <asm/cache.h>
 #include <asm/mmu.h>
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
  /*
  * cache flushing routines for kgdb
  */
@@ -45,34 +45,34 @@ kgdb_flush_cache_all:
        iccci   r0,r0           /* iccci invalidates the entire I cache */
        /* dcache */
        addi    r6,0,0x0000     /* clear GPR 6 */
-        addi    r7,r0, 128     /* do loop for # of dcache lines */
+       addi    r7,r0, 128      /* do loop for # of dcache lines */
                                /* NOTE: dccci invalidates both */
-        mtctr   r7              /* ways in the D cache */
+       mtctr   r7              /* ways in the D cache */
 ..dcloop:
-        dccci   0,r6            /* invalidate line */
-        addi    r6,r6, 32      /* bump to next line */
-        bdnz    ..dcloop
+       dccci   0,r6            /* invalidate line */
+       addi    r6,r6, 32       /* bump to next line */
+       bdnz    ..dcloop
        blr
 
        .globl  kgdb_flush_cache_range
 kgdb_flush_cache_range:
-       li      r5,CFG_CACHELINE_SIZE-1
+       li      r5,L1_CACHE_BYTES-1
        andc    r3,r3,r5
        subf    r4,r3,r4
        add     r4,r4,r5
-       srwi.   r4,r4,CFG_CACHELINE_SHIFT
+       srwi.   r4,r4,L1_CACHE_SHIFT
        beqlr
        mtctr   r4
        mr      r6,r3
 1:     dcbst   0,r3
-       addi    r3,r3,CFG_CACHELINE_SIZE
+       addi    r3,r3,L1_CACHE_BYTES
        bdnz    1b
        sync                    /* wait for dcbst's to get to ram */
        mtctr   r4
 2:     icbi    0,r6
-       addi    r6,r6,CFG_CACHELINE_SIZE
+       addi    r6,r6,L1_CACHE_BYTES
        bdnz    2b
        SYNC
        blr
 
-#endif /* CFG_CMD_KGDB */
+#endif