/*-----------------------------------------------------------------------------+
+ | This source code is dual-licensed. You may use it under the terms of the
+ | GNU General Public License version 2, or under the license below.
|
| This source code has been made available to you by IBM on an AS-IS
| basis. Anyone receiving this source is licensed under IBM
|
+-----------------------------------------------------------------------------*/
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <405_mal.h>
#include <miiphy.h>
-#undef ET_DEBUG
+#if !defined(CONFIG_PHY_CLK_FREQ)
+#define CONFIG_PHY_CLK_FREQ 0
+#endif
+
/***********************************************************/
/* Dump out to the screen PHY regs */
/***********************************************************/
u16 adv;
miiphy_read (devname, addr, PHY_ANAR, &adv);
- adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
- PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
- PHY_ANLPAR_10);
+ adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX |
+ PHY_ANLPAR_10FD | PHY_ANLPAR_10);
miiphy_write (devname, addr, PHY_ANAR, adv);
miiphy_read (devname, addr, PHY_1000BTCR, &adv);
/***********************************************************/
/* read a phy reg and return the value with a rc */
/***********************************************************/
-unsigned int miiphy_getemac_offset (void)
+/* AMCC_TODO:
+ * Find out of the choice for the emac for MDIO is from the bridges,
+ * i.e. ZMII or RGMII as approporiate. If the bridges are not used
+ * to determine the emac for MDIO, then is the SDR0_ETH_CFG[MDIO_SEL]
+ * used? If so, then this routine below does not apply to the 460EX/GT.
+ *
+ * sr: Currently on 460EX only EMAC0 works with MDIO, so we always
+ * return EMAC0 offset here
+ * vg: For 460EX/460GT if internal GPCS PHY address is specified
+ * return appropriate EMAC offset
+ */
+unsigned int miiphy_getemac_offset(u8 addr)
{
-#if (defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)) && defined(CONFIG_NET_MULTI)
+#if (defined(CONFIG_440) && \
+ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+ !defined(CONFIG_460EX) && !defined(CONFIG_460GT)) && \
+ defined(CONFIG_NET_MULTI)
unsigned long zmii;
unsigned long eoffset;
/* Need to find out which mdi port we're using */
- zmii = in_be32((void *)ZMII_FER);
+ zmii = in_be32((void *)ZMII0_FER);
if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0)))
/* using port 0 */
/* None of the mdi ports are enabled! */
/* enable port 0 */
zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
- out_be32((void *)ZMII_FER, zmii);
+ out_be32((void *)ZMII0_FER, zmii);
eoffset = 0;
/* need to soft reset port 0 */
- zmii = in_be32((void *)EMAC_M0);
- zmii |= EMAC_M0_SRST;
- out_be32((void *)EMAC_M0, zmii);
+ zmii = in_be32((void *)EMAC0_MR0);
+ zmii |= EMAC_MR0_SRST;
+ out_be32((void *)EMAC0_MR0, zmii);
}
return (eoffset);
return 0x100;
#endif
- return 0;
-#endif
-}
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ u32 eoffset = 0;
-int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
- unsigned short *value)
-{
- unsigned long sta_reg; /* STA scratch area */
- unsigned long i;
- unsigned long emac_reg;
-
- emac_reg = miiphy_getemac_offset ();
- /* see if it is ready for 1000 nsec */
- i = 0;
-
- /* see if it is ready for sec */
- while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) ==
- EMAC_STACR_OC_MASK) {
- udelay (7);
- if (i > 5) {
-#ifdef ET_DEBUG
- sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
- printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
- printf ("read err 1\n");
-#endif
- return -1;
- }
- i++;
- }
- sta_reg = reg; /* reg address */
- /* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EX)
-#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
- sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
-#else
- sta_reg |= EMAC_STACR_READ;
+ switch (addr) {
+#if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
+ case CONFIG_GPCS_PHY1_ADDR:
+ if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x100)))
+ eoffset = 0x100;
+ break;
#endif
-#else
- sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
+#if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
+ case CONFIG_GPCS_PHY2_ADDR:
+ if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x300)))
+ eoffset = 0x300;
+ break;
#endif
-
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
- !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
- !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
- !defined(CONFIG_405EX)
- sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
+#if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
+ case CONFIG_GPCS_PHY3_ADDR:
+ if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x400)))
+ eoffset = 0x400;
+ break;
#endif
- sta_reg = sta_reg | (addr << 5); /* Phy address */
- sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
- out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
-#ifdef ET_DEBUG
- printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
+ default:
+ eoffset = 0;
+ break;
+ }
+ return eoffset;
#endif
- sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
-#ifdef ET_DEBUG
- printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
+ return 0;
#endif
+}
+
+static int emac_miiphy_wait(u32 emac_reg)
+{
+ u32 sta_reg;
+ int i;
+
+ /* wait for completion */
i = 0;
- while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
- udelay (7);
- if (i > 5)
+ do {
+ sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
+ if (i++ > 5) {
+ debug("%s [%d]: Timeout! EMAC0_STACR=0x%0x\n", __func__,
+ __LINE__, sta_reg);
return -1;
+ }
+ udelay(10);
+ } while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK);
- i++;
- sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
-#ifdef ET_DEBUG
- printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
-#endif
- }
- if ((sta_reg & EMAC_STACR_PHYE) != 0)
- return -1;
-
- *value = *(short *)(&sta_reg);
return 0;
+}
-} /* phy_read */
-
-/***********************************************************/
-/* write a phy reg and return the value with a rc */
-/***********************************************************/
-
-int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg,
- unsigned short value)
+static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
{
- unsigned long sta_reg; /* STA scratch area */
- unsigned long i;
- unsigned long emac_reg;
+ u32 emac_reg;
+ u32 sta_reg;
- emac_reg = miiphy_getemac_offset ();
- /* see if it is ready for 1000 nsec */
- i = 0;
+ emac_reg = miiphy_getemac_offset(addr);
- while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) ==
- EMAC_STACR_OC_MASK) {
- if (i > 5)
- return -1;
+ /* wait for completion */
+ if (emac_miiphy_wait(emac_reg) != 0)
+ return -1;
- udelay (7);
- i++;
- }
- sta_reg = 0;
sta_reg = reg; /* reg address */
- /* set clock (50Mhz) and read flags */
+
+ /* set clock (50MHz) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
- sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
+ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd;
#else
- sta_reg |= EMAC_STACR_WRITE;
+ sta_reg |= cmd;
#endif
#else
- sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
+ sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ;
#endif
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
- !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
- !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
- !defined(CONFIG_405EX)
- sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
-#endif
- sta_reg = sta_reg | ((unsigned long)addr << 5); /* Phy address */
+ /* Some boards (mainly 405EP based) define the PHY clock freqency fixed */
+ sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
+ sta_reg = sta_reg | ((u32)addr << 5); /* Phy address */
sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
- memcpy (&sta_reg, &value, 2); /* put in data */
+ if (cmd == EMAC_STACR_WRITE)
+ memcpy(&sta_reg, &value, 2); /* put in data */
- out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
+ out_be32((void *)EMAC0_STACR + emac_reg, sta_reg);
+ debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
/* wait for completion */
- i = 0;
- sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
-#ifdef ET_DEBUG
- printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
-#endif
- while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
- udelay (7);
- if (i > 5)
- return -1;
-
- i++;
- sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
-#ifdef ET_DEBUG
- printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
-#endif
- }
+ if (emac_miiphy_wait(emac_reg) != 0)
+ return -1;
+ debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
if ((sta_reg & EMAC_STACR_PHYE) != 0)
return -1;
return 0;
+}
+
+int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
+{
+ unsigned long sta_reg;
+ unsigned long emac_reg;
+
+ emac_reg = miiphy_getemac_offset(addr);
+
+ if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
+ return -1;
+
+ sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
+ *value = sta_reg >> 16;
-} /* phy_write */
+ return 0;
+}
+
+/***********************************************************/
+/* write a phy reg and return the value with a rc */
+/***********************************************************/
+
+int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value);
+}