ppc/85xx: add cpu init config file for boot from NAND

[u-boot] / cpu / ppc4xx / miiphy.c

diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index c8827201e9861e3261de443bb26d59cacdfa7bca..fa3bfc8d9f51f4e438613c9462424e18e39774d7 100644 (file)
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -1,4 +1,6 @@
 /*-----------------------------------------------------------------------------+
+  |   This source code is dual-licensed.  You may use it under the terms of the
+  |   GNU General Public License version 2, or under the license below.
   |
   |      This source code has been made available to you by IBM on an AS-IS
   |      basis.  Anyone receiving this source is licensed under IBM
@@ -180,8 +182,10 @@ int phy_setup_aneg (char *devname, unsigned char addr)
  *
  * sr: Currently on 460EX only EMAC0 works with MDIO, so we always
  * return EMAC0 offset here
+ * vg: For 460EX/460GT if internal GPCS PHY address is specified
+ * return appropriate EMAC offset
  */
-unsigned int miiphy_getemac_offset (void)
+unsigned int miiphy_getemac_offset(u8 addr)
 {
 #if (defined(CONFIG_440) && \
     !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
@@ -233,6 +237,35 @@ unsigned int miiphy_getemac_offset (void)
                return 0x100;
 #endif
 
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+       u32 eoffset = 0;
+
+       switch (addr) {
+#if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
+       case CONFIG_GPCS_PHY1_ADDR:
+               if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x100)))
+                       eoffset = 0x100;
+               break;
+#endif
+#if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
+       case CONFIG_GPCS_PHY2_ADDR:
+               if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x300)))
+                       eoffset = 0x300;
+               break;
+#endif
+#if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
+       case CONFIG_GPCS_PHY3_ADDR:
+               if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x400)))
+                       eoffset = 0x400;
+               break;
+#endif
+       default:
+               eoffset = 0;
+               break;
+       }
+       return eoffset;
+#endif
+
        return 0;
 #endif
 }
@@ -262,7 +295,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
        u32 emac_reg;
        u32 sta_reg;
 
-       emac_reg = miiphy_getemac_offset();
+       emac_reg = miiphy_getemac_offset(addr);
 
        /* wait for completion */
        if (emac_miiphy_wait(emac_reg) != 0)
@@ -270,7 +303,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
 
        sta_reg = reg;          /* reg address */
 
-       /* set clock (50Mhz) and read flags */
+       /* set clock (50MHz) and read flags */
 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
@@ -311,13 +344,13 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
        unsigned long sta_reg;
        unsigned long emac_reg;
 
-       emac_reg = miiphy_getemac_offset ();
+       emac_reg = miiphy_getemac_offset(addr);
 
        if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
                return -1;
 
        sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
-       *value = *(u16 *)(&sta_reg);
+       *value = sta_reg >> 16;
 
        return 0;
 }