Merge with git+ssh://sr@pollux.denx.org/home/sr/git/u-boot/denx/.git

[u-boot] / cpu / ppc4xx / start.S

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 5a1ab386b1809ad98bd105a000d93c496dabddb2..200f7b31adfe1dc394949affec7f22444da70332 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -173,9 +173,9 @@
 
 /**************************************************************************/
 _start_440:
-        /*--------------------------------------------------------------------+
-        | 440EPX BUP Change - Hardware team request
-        +--------------------------------------------------------------------*/
+       /*--------------------------------------------------------------------+
+       | 440EPX BUP Change - Hardware team request
+       +--------------------------------------------------------------------*/
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
        sync
        nop
@@ -204,6 +204,18 @@ _start_440:
        mfspr   r1,mcsr
        mtspr   mcsr,r1
 #endif
+
+       /*----------------------------------------------------------------*/
+       /* CCR0 init */
+       /*----------------------------------------------------------------*/
+       /* Disable store gathering & broadcast, guarantee inst/data
+       * cache block touch, force load/store alignment
+       * (see errata 1.12: 440_33)
+       */
+       lis     r1,0x0030       /* store gathering & broadcast disable */
+       ori     r1,r1,0x6000    /* cache touch */
+       mtspr   ccr0,r1
+
        /*----------------------------------------------------------------*/
        /* Initialize debug */
        /*----------------------------------------------------------------*/
@@ -225,17 +237,6 @@ _start_440:
        mtspr   dbsr,r1         /* Clear all valid bits */
 skip_debug_init:
 
-       /*----------------------------------------------------------------*/
-       /* CCR0 init */
-       /*----------------------------------------------------------------*/
-       /* Disable store gathering & broadcast, guarantee inst/data
-       * cache block touch, force load/store alignment
-       * (see errata 1.12: 440_33)
-       */
-       lis     r1,0x0030       /* store gathering & broadcast disable */
-       ori     r1,r1,0x6000    /* cache touch */
-       mtspr   ccr0,r1
-
 #if defined (CONFIG_440SPE)
        /*----------------------------------------------------------------+
        | Initialize Core Configuration Reg1.
@@ -1697,7 +1698,8 @@ ppc405ep_init:
        mtdcr   ebccfgd,r3
 #endif
 
-       addi    r3,0,CPC0_PCI_HOST_CFG_EN
+#ifndef CFG_CPC0_PCI
+       li      r3,CPC0_PCI_HOST_CFG_EN
 #ifdef CONFIG_BUBINGA
        /*
        !-----------------------------------------------------------------------
@@ -1712,6 +1714,9 @@ ppc405ep_init:
        beq     ..pci_cfg_set             /* if not set, then bypass reg write*/
 #endif
        ori     r3,r3,CPC0_PCI_ARBIT_EN
+#else /* CFG_CPC0_PCI */
+       li      r3,CFG_CPC0_PCI
+#endif /* CFG_CPC0_PCI */
 ..pci_cfg_set:
        mtdcr   CPC0_PCI, r3             /* Enable internal arbiter*/
 
@@ -1851,3 +1856,60 @@ pll_wait:
                                     /* execution will continue from the poweron */
                                     /* vector of 0xfffffffc */
 #endif /* CONFIG_405EP */
+
+#if defined(CONFIG_440)
+#define function_prolog(func_name)      .text; \
+                                       .align 2; \
+                                       .globl func_name; \
+                                       func_name:
+#define function_epilog(func_name)      .type func_name,@function; \
+                                       .size func_name,.-func_name
+
+/*----------------------------------------------------------------------------+
+| mttlb3.
++----------------------------------------------------------------------------*/
+       function_prolog(mttlb3)
+       TLBWE(4,3,2)
+       blr
+       function_epilog(mttlb3)
+
+/*----------------------------------------------------------------------------+
+| mftlb3.
++----------------------------------------------------------------------------*/
+       function_prolog(mftlb3)
+       TLBRE(3,3,2)
+       blr
+       function_epilog(mftlb3)
+
+/*----------------------------------------------------------------------------+
+| mttlb2.
++----------------------------------------------------------------------------*/
+       function_prolog(mttlb2)
+       TLBWE(4,3,1)
+       blr
+       function_epilog(mttlb2)
+
+/*----------------------------------------------------------------------------+
+| mftlb2.
++----------------------------------------------------------------------------*/
+       function_prolog(mftlb2)
+       TLBRE(3,3,1)
+       blr
+       function_epilog(mftlb2)
+
+/*----------------------------------------------------------------------------+
+| mttlb1.
++----------------------------------------------------------------------------*/
+       function_prolog(mttlb1)
+       TLBWE(4,3,0)
+       blr
+       function_epilog(mttlb1)
+
+/*----------------------------------------------------------------------------+
+| mftlb1.
++----------------------------------------------------------------------------*/
+       function_prolog(mftlb1)
+       TLBRE(3,3,0)
+       blr
+       function_epilog(mftlb1)
+#endif /* CONFIG_440 */