OMAP3 Move cache routine to cache.S

[u-boot] / cpu / pxa / cpu.c

diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index e27b6b9179575fb38eed44e7c7478ccb1832f6d2..800d120e718bb11a6527223fec3b94855ec17988 100644 (file)
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -35,21 +35,7 @@
 #include <asm/arch/pxa-regs.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-int cpu_init (void)
-{
-       /*
-        * setup up stacks if necessary
-        */
-#ifdef CONFIG_USE_IRQ
-       IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-       FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-       return 0;
-}
+static void cache_flush(void);
 
 int cleanup_before_linux (void)
 {
@@ -60,82 +46,24 @@ int cleanup_before_linux (void)
         * just disable everything that can disturb booting linux
         */
 
-       unsigned long i;
-
        disable_interrupts ();
 
        /* turn off I-cache */
-       asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-       i &= ~0x1000;
-       asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+       icache_disable();
+       dcache_disable();
 
        /* flush I-cache */
-       asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+       cache_flush();
 
        return (0);
 }
 
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-       printf ("resetting ...\n");
+       unsigned long i = 0;
 
-       udelay (50000);                         /* wait 50 ms */
-       disable_interrupts ();
-       reset_cpu (0);
-
-       /*NOTREACHED*/
-       return (0);
-}
-
-/* cache_bit must be either CR_I or CR_C */
-static void cache_enable(uint32_t cache_bit)
-{
-       uint32_t reg;
-
-       reg = get_cr(); /* get control reg. */
-       cp_delay();
-       set_cr(reg | cache_bit);
-}
-
-/* cache_bit must be either CR_I or CR_C */
-static void cache_disable(uint32_t cache_bit)
-{
-       uint32_t reg;
-
-       reg = get_cr();
-       cp_delay();
-       set_cr(reg & ~cache_bit);
-}
-
-void icache_enable(void)
-{
-       cache_enable(CR_I);
-}
-
-void icache_disable(void)
-{
-       cache_disable(CR_I);
-}
-
-int icache_status(void)
-{
-       return (get_cr() & CR_I) != 0;
-}
-
-/* we will never enable dcache, because we have to setup MMU first */
-void dcache_enable (void)
-{
-       return;
-}
-
-void dcache_disable (void)
-{
-       return;
-}
-
-int dcache_status (void)
-{
-       return 0;                                       /* always off */
+       asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 }
 
 #ifndef CONFIG_CPU_MONAHANS