Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xx

[u-boot] / cpu / pxa / start.S

diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S
index ffaa30fdc585417e35c6a234ee8e437ff11533ad..23005e20f97af1884aa55da7a54b20fbc58f23bc 100644 (file)
--- a/cpu/pxa/start.S
+++ b/cpu/pxa/start.S
@@ -57,7 +57,7 @@ _fiq:                 .word fiq
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from RAM!
- * - relocate armboot to ram
+ * - relocate armboot to RAM
  * - setup stack
  * - jump to second stage
  */
@@ -90,7 +90,7 @@ IRQ_STACK_START:
 .globl FIQ_STACK_START
 FIQ_STACK_START:
        .word 0x0badc0de
-#endif
+#endif /* CONFIG_USE_IRQ */
 
 
 /****************************************************************************/
@@ -100,18 +100,18 @@ FIQ_STACK_START:
 /****************************************************************************/
 
 reset:
-       mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
+       mrs     r0,cpsr                 /* set the CPU to SVC32 mode        */
        bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
        orr     r0,r0,#0x13
        msr     cpsr,r0
 
        /*
         * we do sys-critical inits only at reboot,
-        * not when booting from ram!
+        * not when booting from RAM!
         */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
        bl      cpu_init_crit           /* we do sys-critical inits         */
-#endif
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
 
 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 relocate:                              /* relocate U-Boot to RAM           */
@@ -128,9 +128,9 @@ relocate:                           /* relocate U-Boot to RAM           */
 copy_loop:
        ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
        stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end addreee [r2]    */
+       cmp     r0, r2                  /* until source end address [r2]    */
        ble     copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
+#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
 
        /* Set up the stack                                                 */
 stack_setup:
@@ -139,7 +139,7 @@ stack_setup:
        sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 #ifdef CONFIG_USE_IRQ
        sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
+#endif /* CONFIG_USE_IRQ */
        sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 
 clear_bss:
@@ -166,13 +166,13 @@ _start_armboot: .word start_armboot
 /*                                                                         */
 /****************************************************************************/
 /* mk@tbd: Fix this! */
-#ifdef CONFIG_CPU_MONAHANS
+#undef RCSR
 #undef ICMR
 #undef OSMR3
 #undef OSCR
 #undef OWER
 #undef OIER
-#endif
+#undef CCCR
 
 /* Interrupt-Controller base address                                       */
 IC_BASE:          .word           0x40d00000
@@ -193,18 +193,18 @@ OSTIMER_BASE:     .word   0x40a00000
 #ifdef CONFIG_CPU_MONAHANS
 # ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
 #  error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
-# endif
+# endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */
 # ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
 #  define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
-# endif
-#else /* ! CONFIG_CPU_MONAHANS */
+# endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */
+#else /* !CONFIG_CPU_MONAHANS */
 #ifdef CFG_CPUSPEED
 CC_BASE:       .word   0x41300000
 #define CCCR   0x00
 cpuspeed:      .word   CFG_CPUSPEED
-#else
+#else /* !CFG_CPUSPEED */
 #error "You have to define CFG_CPUSPEED!!"
-#endif
+#endif /* CFG_CPUSPEED */
 #endif /* CONFIG_CPU_MONAHANS */
 
        /* takes care the CP15 update has taken place */
@@ -221,7 +221,7 @@ cpu_init_crit:
        ldr     r0, IC_BASE
        mov     r1, #0x00
        str     r1, [r0, #ICMR]
-#else
+#else /* CONFIG_CPU_MONAHANS */
        /* Step 1 - Enable CP6 permission */
        mrc     p15, 0, r1, c15, c1, 0  @ read CPAR
        orr     r1, r1, #0x40
@@ -240,14 +240,14 @@ cpu_init_crit:
        ldr     r1, =CKENB
        ldr     r2, =(CKENB_6_IRQ)
        str     r2, [r1]
-#endif
+#endif /* !CONFIG_CPU_MONAHANS */
 
        /* set clock speed */
 #ifdef CONFIG_CPU_MONAHANS
        ldr     r0, =ACCR
        ldr     r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
        str     r1, [r0]
-#else /* ! CONFIG_CPU_MONAHANS */
+#else /* !CONFIG_CPU_MONAHANS */
 #ifdef CFG_CPUSPEED
        ldr     r0, CC_BASE
        ldr     r1, cpuspeed
@@ -447,7 +447,7 @@ fiq:
        bl      do_fiq                  /* effiction fiq_save_user_regs     */
        irq_restore_user_regs
 
-#else
+#else /* !CONFIG_USE_IRQ */
 
        .align  5
 irq:
@@ -461,7 +461,7 @@ fiq:
        bad_save_user_regs
        bl      do_fiq
 
-#endif
+#endif /* CONFIG_USE_IRQ */
 
 /****************************************************************************/
 /*                                                                         */