Merge git://git.denx.de/u-boot into x1

[u-boot] / cpu / s3c44b0 / start.S

diff --git a/cpu/s3c44b0/start.S b/cpu/s3c44b0/start.S
index b4b7c3f62cec4ba761989c5abd67fa87fe1e752c..f5a3d3ac386ceabe492e91c8ba6bab56a6938cec 100644 (file)
--- a/cpu/s3c44b0/start.S
+++ b/cpu/s3c44b0/start.S
@@ -112,16 +112,17 @@ reset:
         * not when booting from ram!
         */
 
-#ifdef CONFIG_INIT_CRITICAL
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
        bl      cpu_init_crit
        /*
         * before relocating, we have to setup RAM timing
         * because memory timing is board-dependend, you will
-        * find a memsetup.S in your board directory.
+        * find a lowlevel_init.S in your board directory.
         */
-       bl      memsetup
+       bl      lowlevel_init
 #endif
 
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 relocate:                              /* relocate U-Boot to RAM           */
        adr     r0, _start              /* r0 <- current position of code   */
        ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
@@ -151,12 +152,13 @@ vector_copy_loop:
        stmia   r1!, {r3-r10}
        cmp     r0, r2
        ble     vector_copy_loop
+#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
 
        /* Set up the stack                                                 */
 stack_setup:
        ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
-       sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
-       sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
+       sub     r0, r0, #CONFIG_SYS_MALLOC_LEN  /* malloc area                      */
+       sub     r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
 #ifdef CONFIG_USE_IRQ
        sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 #endif
@@ -186,7 +188,7 @@ _start_armboot:     .word start_armboot
 #define WTCON (0x01c00000+0x130000)
 cpu_init_crit:
        /* disable watch dog */
-       ldr     r0, =WTCON
+       ldr     r0, =WTCON
        ldr     r1, =0x0
        str     r1, [r0]
 
@@ -209,7 +211,7 @@ cpu_init_crit:
        ldr     r1, =PLLCON
 
 #if CONFIG_S3C44B0_CLOCK_SPEED==66
-       ldr     r0, =0x34031    /* 66MHz (Quartz=11MHz) */
+       ldr     r0, =0x34031    /* 66MHz (Quartz=11MHz) */
 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
        ldr     r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
 #else