Update CHANGELOG, minor coding style cleanup.

[u-boot] / doc / README.mpc8349emds.ddrecc

diff --git a/doc/README.mpc8349emds.ddrecc b/doc/README.mpc8349emds.ddrecc
index d8edada5654c13c9abc39ac3a8faaf32a65f2893..eb249c3956f15a8dd810ceb2f592418761b166b4 100644 (file)
--- a/doc/README.mpc8349emds.ddrecc
+++ b/doc/README.mpc8349emds.ddrecc
@@ -1,3 +1,24 @@
+Overview
+========
+
+The overall usage pattern for ECC diagnostic commands is the following:
+
+  * (injecting errors is initially disabled)
+
+  * define inject mask (which tells the DDR controller what type of errors
+    we'll be injecting: single/multiple bit etc.)
+
+  * enable injecting errors - from now on the controller injects errors as
+    indicated in the inject mask
+
+IMPORTANT NOTICE: enabling injecting multiple-bit errors is potentially
+dangerous as such errors are NOT corrected by the controller. Therefore caution
+should be taken when enabling the injection of multiple-bit errors: it is only
+safe when used on a carefully selected memory area and used under control of
+the 'ecc test' command (see example 'Injecting Multiple-Bit Errors' below). In
+particular, when you simply set the multiple-bit errors in inject mask and
+enable injection, U-Boot is very likely to hang quickly as the errors will be
+injected when it accesses its code, data etc.
 
 
 Use cases for DDR 'ecc' command:
@@ -131,5 +152,3 @@ Observe that Single-Bit Error is 'on' which means that Single-Bit Error Counter
 reached Single-Bit Error Threshold. Multiple Memory Errors bit is also 'on', that
 is Counter reached Threshold more than one time (it wraps back after reaching
 Threshold).
-
-